What Movellus does

Movellus is a private semiconductor infrastructure IP company founded in 2014 and headquartered in Santa Clara, California. It develops and licenses digital, synthesizable IP blocks that address three physical planes of modern SoCs and chiplets: clocking, power delivery, and on-die telemetry. The company's core proposition is that AI-era chips require infrastructure IP capable of managing voltage droop, fine-grained DVFS, and distributed clocking at sub-3-cycle response times, delivered as portable digital IP rather than analog blocks. Its technology is fully digital and process-portable, enabling integration across advanced nodes and heterogeneous multi-die architectures.

The Aeonic™ product portfolio comprises Aeonic Generate™ (digital PLL clock generation, claimed 8x smaller than fractional analog PLLs), Aeonic Insight™ (on-die telemetry including PDNIQ 2 and droop detector sensors), Aeonic Power™ (integrated on-die voltage regulation with HC and LN variants), Aeonic Connect™ (single-cycle die-to-die signaling at 3–5x lower power than existing standards), and the Aeonic™ Integrated Droop Response System (turnkey sub-3-cycle droop detection and response delivering >10% system power reduction). The portfolio is backed by more than 20 granted US patents covering PLL architecture, droop detection, timing analysis, and die-to-die communication, alongside a registered Aeonic trademark family.

Movellus generates revenue through IP licensing and per-unit royalties, distributed via direct enterprise sales (led by a VP of Worldwide Sales with 30 years of IP industry experience) and through channel partnerships, most notably integration of its adaptive clocking IP into Synopsys' Silicon Lifecycle Management (SLM) IP portfolio. The company targets datacenter (primary), mobile, automotive ADAS, mil/aero (via QuickLogic's rad-hard FPGA program), and edge AI segments. The leadership team combines founder-CEO Mo Faisal (ex-Intel, PMC Sierra), COO Vikram Karvat (ex-Marvell/Cavium/QLogic), CFO Ras Sheffield (former Magma Design Automation IPO CFO), and VP Engineering Saif Alam (ex-AMD, Intel), with strategic investors Intel Capital, SK Hynix, In-Q-Tel, and Stata Venture Partners holding board representation.

Name

Movellus

Legal name

Movellus

Website

https://movellus.com

Company type

Private

Founded year

2014

Operating status

Operating

Headcount range

11–50 employees

Short description

Movellus provides digital, synthesizable semiconductor infrastructure IP — including clock generation (Aeonic Generate™), on-die voltage regulation (Aeonic Power™), telemetry (Aeonic Insight™), and die-to-die signaling (Aeonic Connect™) — licensed to SoC and chiplet designers serving datacenter, mobile, automotive, mil/aero, and edge AI markets.

Ownership category

akta.pro rank

Product category

Semiconductor Infrastructure IP

NAICS

Semiconductor and Related Device Manufacturing (334413)

SIC

Semiconductors & Related Devices (3674), Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF)

akta.pro secondary industries

Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH), AI Hardware IP & Chiplet/Packaging for Accelerators (EDA/IP, advanced packaging) (HDAAAAAL), IP Enablement, Characterization & Porting Services (HDAHAFAI)

Keywords

• Semiconductor IP
• Clock generation IP
• On-die telemetry
• Power delivery IP
• Die-to-die interconnect

Headquarters

HQ city

Santa Clara

HQ country

United States

HQ region

North America

Offices2 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales, Infrastructure

Revenue model

1. IP Licensing and Royalties: Movellus licenses its infrastructure IP (Aeonic clocking, power, and telemetry IP) to semiconductor companies. Revenue is generated through licensing fees and per-unit royalties for integration into customer chips. The Synopsys partnership expands access to Movellus technology via Synopsys channels.

Go-to-market motion3 records

Distribution channels2 records

Marketing channels5 records

Core offering

Movellus develops and licenses the Aeonic™ portfolio of synthesizable digital infrastructure IP for semiconductor chips. Its offerings span three integrated planes — Sensor Plane (Aeonic Insight™ on-die telemetry), Clock Plane (Aeonic Generate™ digital PLL clocking), and Power Plane (Aeonic Power™ on-die voltage regulation) — plus Aeonic Connect™ die-to-die signaling and an integrated droop response system, targeting power, performance, and reliability optimization for AI-era SoCs and chiplets.

Product overview

Movellus is an infrastructure IP company offering the Aeonic™ IP portfolio for optimizing power, performance, and reliability in complex chips for the AI era. The portfolio comprises three integrated planes: Sensor Plane (Aeonic Insight™ for on-die telemetry and observability), Clock Plane (Aeonic Generate™ for digital PLL clocking solutions), and Power Plane (Aeonic Power™ for voltage regulation). Key products include Aeonic Insight™ (including PDNIQ 2 and Droop Detector), Aeonic Generate™ (including AWM3 and CGM variants), Aeonic Power™ (including HC and LN variants), the Aeonic™ Integrated Droop Response System, and Aeonic Connect™ for die-to-die signaling. All products are portable/digital, configurable, customizable, and programmable, targeting datacenter, mobile, automotive, mil/aero, and edge AI market segments.

Differentiator

Problem solved

Functional benefit

Brands

• Aeonic™: Infrastructure IP portfolio brand encompassing clock generation (Aeonic Generate™), on-die telemetry (Aeonic Insight™), power delivery (Aeonic Power™), and droop response (Aeonic Droop™) solutions.
• Aeonic Insight™
• Aeonic Generate™
• Aeonic Droop™
• Aeonic Power™
• Aeonic Connect™
• Aeonic Jumpstart™

Products and services

• Aeonic Insight™ Advanced on-die telemetry IP product for SoCs, offering sensor modules with visibility into power grid, clock health, and SoC security. Features programmable sensors and industry-standard interfaces for integration with third-party silicon analytics platforms; targeted at semiconductor design teams building complex SoCs and chiplets.
• Aeonic Generate™ Digital PLL clock generation IP family delivering synthesizable, area-efficient clocking with high observability for SoC designers. Enables fine-grained droop/DVFS response and distributed clocking architectures, with area roughly 8x smaller than fractional analog PLLs and operation from core VDD supply.
• Aeonic Power™ Power delivery IP family with integrated on-die voltage regulation enabling energy and BOM optimization for SoCs and chiplets. Features highly configurable architecture with PDN-oriented telemetry and high-current (HC) and low-noise (LN) variants.
• Aeonic™ Integrated Droop Response System Turnkey integrated droop detection and response solution that detects and responds to voltage droop in under three high-speed clock cycles, enabling voltage margin reduction and system power savings exceeding 10%. Combines sensor and clock plane elements for SoC designers targeting AI and high-performance computing workloads.
• Aeonic Connect™ Die-to-die signaling IP enabling single-cycle die-to-die interconnect that is 3–5x lower power than existing standards, supporting chiplet architectures for system-on-chip designers.

Quantifiable outcome

• System power reduction of more than 10% through voltage margin reduction via tight coupling of droop detection and response in under three high-speed clock cycles
• +2 more outcomes

Named customers1 record

Segments5 records

Ideal customer profiles2 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature5 records

Partnerships

Two partnerships are on record, tiered major and strategic.

• SynopsysmajorTechnology or Integration · 10 March 2026Movellus adaptive clocking technology integrated into Synopsys Silicon Lifecycle Management (SLM) IP portfolio as SLM Advanced Clock Generator (ACG) IP. The collaboration enables real-time power optimization for SoCs and expands customer access to Movellus technology via Synopsys' global distribution channels.
• QuickLogic CorporationstrategicTechnology or Integration · 9 March 2026Movellus Aeonic Generate clocking IP selected for QuickLogic's Strategic Radiation Hardened (SRH) FPGA program targeting defense and aerospace industries. Partnership aims to deliver domestically sourced and fabricated programmable logic for mission-critical applications, enhancing supply chain resilience.

Scale indicators3 records

Recent moves6 records

Expansion highlights6 records

Broad incumbents

• Synopsys: The largest EDA and semiconductor IP vendor globally, offering DesignWare IP spanning interfaces, processors, analog, and security. Synopsys is simultaneously Movellus's distribution partner (via the SLM IP portfolio) and a broader incumbent across multiple infrastructure IP categories.
• Cadence Design Systems: Major EDA vendor with a growing IP portfolio (Cadence IP) including Tensilica processors, interface, analog, and memory IP. Competes with Movellus across clocking, power, and die-to-die categories as part of broader EDA platform offerings.
• Arm Holdings: Dominant processor IP vendor with expanding infrastructure IP (CMN, NIC) targeting data center and chiplet markets. Overlaps with Movellus in SoC infrastructure and is where Movellus's VP of Sales, David Steer, began his career.

Direct peers

• Arteris: Licensor of network-on-chip (NoC) IP and SoC integration IP, directly addressing similar SoC infrastructure pain points. Co-participated with Movellus in the 2026 In-Silicon Observability Roundtable, signaling overlapping customer base and competitive overlap in chiplet/SoC IP.
• Rambus: Semiconductor IP company licensing memory and interface IP (DDR, HBM, PCIe, CXL) to chipmakers. Operates a similar IP-licensing and royalty business model and overlaps with Movellus in high-performance infrastructure IP for advanced SoCs.
• CEVA: Licensor of DSP, AI processor, and wireless platform IP, operating under a licensing-plus-royalty model very similar to Movellus. Targets semiconductor and OEM customers with infrastructure-class IP.
• Alphawave Semi: Licensor of high-speed connectivity IP including SerDes, die-to-die, and UCIe PHYs. Direct overlap with Movellus's Aeonic Connect die-to-die solution and analogous customer base among hyperscaler and AI silicon designers.
• Silicon Creations: Specialist IP vendor for PLLs, SerDes, and high-speed mixed-signal IP. Competes with Movellus in clocking IP categories and shares the licensing-plus-royalty business model serving fabless semiconductor customers across advanced nodes.
• Mobiveil: Semiconductor IP company specializing in memory, interconnect, and interface IP (DDR, NAND, CXL). Comparable infrastructure IP licensing model and overlapping customer base among SoC designers.
• SiFive: RISC-V processor IP licensor operating a pure IP-licensing business model serving AI and data center chip designers. Comparable go-to-market motion (enterprise IP licensing, foundry partnerships) and overlapping customer profile in modern SoC design.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

• Xx.com/movellus
• LinkedInlinkedin.com/company/movellus

Revenue estimate

Valuation estimate

Number of profiles

Profiles5 records

Funding overview

Funding rounds9 records

Investors12 records

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Movellus