Name

Nuclei System Technology

Legal name

芯来智融半导体科技（上海）有限公司

Website

https://nucleisys.com

Company type

Private

Founded year

2018

Operating status

Operating

Headcount range

51–100 employees

Ownership category

akta.pro rank

Product category

Processor IP

NAICS

Semiconductor and Other Electronic Component Manufacturing (3344), Semiconductor and Other Electronic Component Manufacturing (33441)

SIC

Semiconductors & Related Devices (3674), Electronic Components, Nec (3679), Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF)

akta.pro secondary industries

Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH), Automotive & Safety-Certified Processors (ADAS/Domain/ASIL MCUs) (HDAHAJAJ), Real-Time & Industrial Control Processors (RT MCUs/PLC-class SoCs) (HDAHAJAL), Audio, Imaging & Multimedia SoCs (ISP/Codec/Display) (HDAHABAH)

Keywords

• RISC-V processor IP
• CPU IP cores
• SoC subsystem design
• Automotive functional safety
• Semiconductor IP licensing

Headquarters

HQ city

Shanghai

HQ country

China

HQ region

Asia

Offices7 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Technology or R&D, Personnel, Marketing or Sales, Operations, Infrastructure

Revenue model

1. RISC-V CPU IP Licensing: Traditional per-project IP licensing of RISC-V processor cores to semiconductor companies. Customers pay for the right to use Nuclei's CPU IP in their chip designs.
2. RISC-V IP 2.0 — '随芯包' (Per-Chip Package) Subscription: Subscription-based model offering access to a suite of CPU IP models (N100, N200, N300, N600, N900, U600, U900, NX600, NX900, UX600, UX900) for an annual subscription fee. Designed to lower adoption barriers, reduce per-project costs, and streamline authorization timelines for Chinese SoC companies.
3. SoC Subsystem Solutions: Complete pre-integrated processing sub-systems (including interrupt controllers, bus fabrics, debug logic) sold as turnkey subsystem packages. Targets to eliminate months of integration labor, generating revenue through subsystem-level licensing and customization.
4. Automotive Functional Safety and Security Packages: Specialized safety (ASIL-D, ASIL-B) and security packages for automotive and security-focused customers. Includes comprehensive functional safety deliverables, documentation, and support services for chip certification processes.

Pricing tiers

Go-to-market motion4 records

Distribution channels5 records

Marketing channels9 records

Core offering

Nuclei System Technology designs, develops, and licenses RISC-V processor IP cores and pre-integrated SoC subsystems to semiconductor companies. Its portfolio spans ultra-low-power 32-bit microcontrollers (N/U series) to high-performance 64-bit multi-core application processors (UX series), with specialized variants for automotive functional safety (NA, ISO 26262 ASIL-D), security (NS), and AI acceleration (NI with RVV 1.0). The company sells these as licensed IP under both per-project licensing and a subscription-based "随芯包" (per-chip package) model.

Product overview

Nuclei System Technology offers a comprehensive RISC-V processor IP portfolio as both individual CPU cores and integrated subsystem solutions. The core IP lineup consists of four general-purpose processor series — N/U (32-bit ultra-low-power to high-performance), NX/UX (64-bit application processors with MMU for Linux), and the flagship UX1000 series (out-of-order high-performance) — plus three specialized series: NS (security with anti-side-channel protection), NA (automotive with ISO 26262 ASIL-D certification), and NI (AI with RVV vector processing up to 1024-bit). Complementing the CPU IPs, Nuclei provides pre-integrated subsystems including an HSM (Hardware Security Module) subsystem, an Automotive subsystem, and an AI subsystem, all configurable via the web-based Subsystem Architector tool. The software platform includes Nuclei Studio IDE, SDK (supporting baremetal and RTOS), NMSIS framework (Core, DSP, NN), toolchains (GCC/LLVM, OpenOCD, QEMU), and development boards. The 'RISC-V IP 2.0' commercial model offers both a subscription-based '随芯包' IP licensing model and a '子系统' SoC-level subsystem IP package, serving over 80 subsystem customers. The ecosystem supports commercial tools from IAR, Lauterbach, SEGGER, TASKING, and Terapines, as well as RTOS (FreeRTOS, RT-Thread) and AI frameworks (TensorFlow Lite Micro, TinyMaix, Tengine-Lite) optimized for Nuclei cores.

Differentiator

Problem solved

Functional benefit

Products and services

• N/U Series Processors 32-bit RISC-V general-purpose processor cores ranging from ultra-low-power N100 (2-stage pipeline) to high-performance N900 (9-stage dual-issue pipeline), supporting SV32 MMU. Targets edge computing, IoT, MCU, and embedded applications. Equivalent to ARM Cortex-M0/M3/M4/M7.
• NX/UX Series Processors 64-bit RISC-V application processor series supporting SV39/SV48 MMU for Linux and heavy OS workloads. NX series targets high-performance embedded; UX series adds full application processor capability with MMU.
• UX1000 Series Processors Out-of-order 64-bit RISC-V application processor series with multi-decoding width (UX1030/UX1040/UX1060 with 3/4/6 decoders), out-of-order issue and execution; supports up to 8 cores per cluster with cache coherence. Targets network processing, AI, autonomous driving, and data center acceleration.
• NS Series Security Processors Security-focused RISC-V processor line (NS100, NS300, NS600) with anti-side-channel attack protection including parity-protected key registers, data path randomization, secure state monitoring, secure debug, and interrupt vector table remapping. Targets SIM cards, smart cards, financial payments, IoT security.
• NA Series Automotive Processors Automotive-grade RISC-V processor line (NA300, NA900) with ISO 26262 ASIL-D and ASIL-B functional safety certifications from exida. Provides complete functional safety delivery package. Globally first and only RISC-V CPU IP with ASIL-D certification. Targets automotive MCU/ECU, gateway, LiDAR, and ADAS.
• NI Series AI Processors AI-dedicated RISC-V processor series (NI900) with configurable RISC-V Vector (RVV 1.0) processing unit; VLEN up to 1024-bit; delivers hundreds-of-times INT8 and dozens-of-times FP32 performance gains over scalar; supports NPU coupling via IOCP and NICE custom instructions. Targets edge AI inference and AIoT.
• HSM Security Subsystem Pre-integrated Hardware Security Module (HSM) subsystem built on Nuclei RISC-V CPUs (N300/NS300/NA300), including symmetric/asymmetric cryptography (AES, SM4, RSA, SM2), hash modules, TRNG, two-level secure boot, and mailbox-based host communication. Targets automotive (EVITA Full), network security, industrial control.
• Automotive Subsystem Pre-integrated automotive processing subsystem based on NA series automotive-grade RISC-V cores, including AUTOSAR support (via Hirain INTEWORK-EAS), MCAL, and functional safety packages. Targets automotive MCU, gateway, LiDAR, and ADAS chip design.
• AI Subsystem Pre-integrated AI processing subsystem based on NI series RISC-V cores with vector processing unit; integrates NMSIS-NN library, TensorFlow Lite Micro, and TinyMaix for AI inference acceleration. Targets edge AI and AIoT applications.
• Subsystem Architector Web-based graphical configuration tool that lets customers select CPU core, bus fabric, interrupt controller, debug logic, and peripheral configurations to produce a complete pre-integrated subsystem package.
• Nuclei Studio IDE Eclipse-based integrated development environment for Nuclei RISC-V processors, supporting Windows and Linux. Integrates NPK package manager, Nuclei SDK, and third-party toolchain support including IAR, SEGGER, and Terapines ZCC.
• Nuclei SDK Full software development kit for Nuclei 200/300/600/900/1000 series CPUs, supporting baremetal and RTOS (FreeRTOS, uCOS-II, RT-Thread, ThreadX); integrates NMSIS framework, NMSIS-DSP, and NMSIS-NN libraries.
• Chip Development Board Hardware development board for chip prototype validation using Nuclei RISC-V cores, supporting RTL simulation, FPGA verification, and software development.
• FPGA Development Board Xilinx FPGA-based development board (DDR200T) for Nuclei RISC-V processor evaluation, enabling hardware-software co-development and validation before tape-out.
• Debugger

Quantifiable outcome

• Several billion units shipped to date, with nearly 1 billion shipped per latest company data
• +9 more outcomes

Named customers27 records

Segments6 records

Ideal customer profiles6 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration15 records

AI capability7 records

Feature11 records

Partnerships

17 partnerships are on record, tiered minor, core and flagship.

• OSYX TechnologiesminorStrategic or Co-development Partner · 4 March 2026OSYX — provider of Bao open-source hypervisor — formed strategic partnership with Nuclei to integrate Bao secure, deterministic virtualization hypervisor into Nuclei's RISC-V processor product family. Supports RISC-V virtualization strategy.
• TASKINGcoreTechnology or Integration · 21 January 2026TASKING's flagship debug and analysis tool winIDEA now supports Nuclei System Technology's RISC-V IP for automotive and safety-critical application scenarios, enabling efficient, visual, traceable software debugging for RISC-V architecture developers.
• Quintauris (SiFive/Bosch/BMW/Infineon/NXP/Qualcomm Joint Venture)flagshipStrategic or Co-development Partner · 12 January 2026Strategic partnership to standardize high-performance RISC-V IP across next-generation automotive zonal controllers and ADAS platforms. Quintauris (backed by Bosch, BMW, Infineon, NXP, Qualcomm) and Nuclei, alongside SiFive, are the RISC-V IP providers who achieved ISO 26262 ASIL-D certification. This marks RISC-V's emergence as the third pillar of automotive computing, targeting 25% of new automotive silicon unit shipments.
• VeriSilicon (芯原微电子)coreStrategic or Co-development Partner · 12 December 2025VeriSilicon attempted to acquire 97.007% of Nuclei System Technology for undisclosed amount. The acquisition was terminated on December 12 citing misalignment on key terms and market conditions. Despite failed M&A, VeriSilicon remains a partner listed on Nuclei's website (partner logo displayed).
• 兆松科技 (Zhaosong/Terapines)coreTechnology or Integration · 9 June 2025Zhaosong ZCC 4.0.0 compiler fully supports Nuclei NA300/900 series with FuSa version achieving ISO 26262 certification. ZCC delivers 22% CoreMark and 35% Dhrystone performance improvement vs GCC 14.2.0. ZCC 4.0 adds support for Nuclei's custom Xxlvqmacc extension instructions.
• 兆松科技 (Zhaosong/Terapines)coreTechnology or Integration · 19 April 2024Zhaosong ZCC toolchain supports Nuclei RISC-V processor cores including custom extensions Xxldsp and Xxlcz. Achieved up to 9.38% CoreMark performance improvement (O3) and up to 20.78% code density improvement (Os) across Nuclei series.
• 经纬恒润 (Hirain)coreTechnology or Integration · 11 April 2024经纬恒润 AUTOSAR software product INTEWORK-EAS successfully adapted to Nuclei NA series automotive RISC-V cores on HP060 development board. Creates flexible, reliable, high-performance, and secure automotive solutions reducing AUTOSAR adaptation cost and cycle time.
• IAR SystemscoreTechnology or Integration · 9 April 2024IAR Embedded Workbench for RISC-V certified for ISO 26262 functional safety (10 safety standards including ISO 26262, IEC 61508) fully supports Nuclei NA series automotive-grade RISC-V processors. IAR provides golden standard compiler and debugger toolchain for Nuclei-based chip development.
• MachineWarecoreTechnology or Integration · 9 April 2024MachineWare SIM-V ultra-fast RISC-V emulator enables simulation of high-performance MCU/SoC systems before physical prototypes are available. Partnership with IAR and Nuclei enables seamless switching between virtual and physical SoC for early software development and HIL testing.
• Siemens EDA (Tessent)coreTechnology or Integration · 1 March 2024Siemens EDA Tessent Enhanced Trace Encoder solution fully supports Nuclei RISC-V processor cores, providing real-time CPU program execution monitoring. Encodes instruction and data trace at SoC level in highly compressed format per RISC-V Foundation E-Trace standard. Supports custom instruction debugging.
• SEGGER MicrocontrollercoreTechnology or IntegrationSEGGER Embedded Studio deeply optimized for Nuclei Processors, supporting 200/300/600/900/1000 series. SEGGER's emRun runtime library integrated into Nuclei Studio IDE.
• LauterbachcoreTechnology or IntegrationLauterbach development tools deeply optimized for Nuclei processors supporting 200/300/600/900 series. Provides debug and trace capabilities for Nuclei processors. In 2026, completed world's first RISC-V Data Trace solution with Nuclei.
• RISC-V Foundation / RISC-V InternationalcoreOthersMember of RISC-V Foundation (now RISC-V International) contributing to RISC-V standard specifications. Co-author of RVA23 profile for automotive. Founder Bob Hu was primary catalyst for RISC-V in Asia, authoring first Chinese textbooks.
• China RISC-V Industry Alliance (中国RISC-V产业联盟)coreOthersFounding and active member. CEO 彭剑英 served as Secretary General of the alliance. Nuclei contributes to standards development, ecosystem building, and RISC-V adoption in China.
• UCIe (Universal Chiplet Interconnect Express) AlliancecoreOthersNuclei joined UCIe consortium as one of the first Chinese RISC-V CPU IP companies to do so, positioning for Chiplet ecosystem evolution and preparing for next-generation heterogeneous integration.
• 华东师范大学 SOLE实验室 (ECNU SOLE Lab)minorStrategic or Co-development PartnerAcademic research collaboration on LLVM/CLANG compiler optimization and program performance tuning for RISC-V processors. Joint research produced LLVM optimization contributions, FFmpeg x264 analysis, CoreMark jump threading improvements (18% score boost), and SPEC CPU 2006 compilation optimization.
• SiFiveflagshipStrategic or Co-development PartnerAlongside Nuclei, SiFive achieved ISO 26262 ASIL-D certification. Both companies are RISC-V IP providers selected by Quintauris for automotive standardization. Co-partners in the RVA23 profile development and automotive RISC-V ecosystem building.

Scale indicators8 records

Recent moves8 records

Expansion highlights7 records

Direct peers

• SiFive: US-based RISC-V CPU IP company with comparable Application, Automotive, and Intelligence product lines. SiFive is Nuclei's most direct global competitor — both are ASIL-D certified and both are founding IP providers in the Quintauris automotive RISC-V coalition alongside Bosch, BMW, Infineon, NXP, and Qualcomm.
• Andes Technology: Taiwan-based RISC-V processor IP provider with comparable N/X/A-series product portfolio targeting embedded, AI edge, and automotive applications. Andes is a publicly-listed direct competitor also offering ASIL-D certified cores and is the dominant RISC-V IP vendor in Taiwan's MCU and IoT chip ecosystem.

Broad incumbents

• ARM: UK-based dominant CPU IP incumbent whose Cortex-M, Cortex-R, and Cortex-A product lines define the MCU, real-time, and application-processor categories Nuclei targets. ARM is the primary incumbent Nuclei's RISC-V IP is positioned to displace in safety-critical automotive and AIoT sockets.
• Synopsys (ARC Processor IP): Synopsys ARC processor IP is a comparable CPU IP offering for embedded and application processor use cases, sold as part of Synopsys' broader EDA and IP portfolio. Competes with Nuclei for MCU, AIoT, and DSP design wins where Synopsys' full EDA stack is preferred.
• Cadence (Tensilica): Cadence's Tensilica processor IP offers configurable DSP and AI cores targeting audio, vision, and baseband — categories that overlap with Nuclei's NI series vector-extended cores and N-series industrial DSP applications. Broad incumbent in the configurable processor IP category.
• Imagination Technologies: UK-based IP vendor with CPU (MIPS) and GPU IP offerings. Imagination's recent RISC-V investments and Catapult RISC-V cores overlap with Nuclei's high-performance UX series positioning in AI, automotive, and data center workloads.

Emerging players

• Ventana Micro Systems: US-based RISC-V chiplet and high-performance application processor IP startup targeting data center and automotive. Comparable to Nuclei's UX1000 series in performance positioning but with a US-headquartered, chiplet-focused go-to-market that competes in overlapping customer RFQs.
• Tenstorrent: AI chip company using RISC-V-based Ascalon cores for its data center and edge AI accelerators. While primarily a chip company rather than IP vendor, Tenstorrent is a notable emerging RISC-V ecosystem participant whose in-house RISC-V efforts represent an alternative to licensing third-party IP like Nuclei's NI series.

Others

• VeriSilicon: China-based IP and chip design services platform that attempted to acquire 97% of Nuclei in 2025 (terminated December 2025). VeriSilicon offers its own SiP and IP integration services and is a strategic peer in the Chinese semiconductor IP ecosystem, with overlapping customer relationships in Chinese SoC design houses.
• RISC-V International: Global standards organization for the RISC-V ISA. Nuclei is a contributing member of RISC-V International and a co-author of the RVA23 profile. Not a competitor but a critical ecosystem participant whose standards decisions directly affect Nuclei's product roadmap.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat6 records

Key risks7 records

Key highlights7 records

Customer concentration

• GitHubgithub.com/Nuclei-Software
• LinkedInlinkedin.com/company/nucleisys

Compliance4 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles5 records

Funding overview

Funding rounds4 records

Investors16 records

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Nuclei System Technology