What Excellicon does

Excellicon is a United States-based electronic design automation (EDA) software company founded in 2009 and headquartered in Laguna Hills, California. The company develops a specialized platform for timing constraint management used in integrated circuit and system-on-chip (SoC) design. Its technology covers creating, compiling, certifying, formally validating, budgeting, and managing timing constraints across multiple design modes, and pairs that constraint flow with an early-design planning capability that enables RTL-level feasibility analysis, PPA estimation, partitioning optimization, and early floorplan generation. Following Siemens AG's May 2025 acquisition announcement, Excellicon's tools were re-launched within Siemens EDA under the Gencellicon brand, consisting of four integrated modules: Constraints Builder, Constraints Certifier, Clock Analyzer, and Chip Planner.

The platform is designed to accelerate design closure by adopting a "correct-by-construction" approach to Synopsys Design Constraints (SDC) that reduces iteration between RTL, synthesis, and place-and-route stages. It includes formal and SVA-based exception verification, timing budget generation across design blocks, timing equivalency checking, and pre-CTS/post-CTS clock tree analysis with skew group and exception guidance generation. The technology is integrated with Siemens EDA's broader portfolio, including Questa (verification), Tessent (DFT), Aprisa (digital implementation), and PowerPro (power), to deliver a unified SoC implementation flow.

Pre-acquisition, Excellicon operated as a privately-held, bootstrapped software company (11-50 employees) with no disclosed funding rounds or revenue figures, serving semiconductor and IC design companies horizontally across the SoC market. Pricing was not publicly disclosed. Post-acquisition, the company no longer operates as an independent commercial entity; its products are now marketed, sold, and supported through Siemens EDA's global distribution infrastructure. Founder Peter Petrov continues in a leadership capacity (Founder & CEO/CTO).

Name

Excellicon

Website

https://excellicon.com

Company type

Private

Founded year

2009

Operating status

Acquired

Headcount range

11–50 employees

Short description

Excellicon, founded in 2009 in Laguna Hills, California, is an EDA software vendor specializing in timing constraint management for SoC and integrated circuit design. Acquired by Siemens AG in May 2025, its product suite was rebranded as Gencellicon within Siemens EDA.

Ownership category

akta.pro rank

Product category

Electronic Design Automation (EDA) Software

NAICS

Computer Systems Design Services (541512)

SIC

Services-Prepackaged Software (7372)

akta.pro primary industry

EDA Software Platforms (Digital Implementation, Verification & Signoff) (HDAHAFAA)

akta.pro secondary industry

Design Services & ASIC/SoC Implementation (EDA-Adjacent) (HDAHAFAL)

Keywords

• Timing constraint management
• EDA software tools
• SoC design closure
• SDC verification
• RTL floorplanning

Headquarters

HQ city

Laguna Hills

HQ country

United States

HQ region

North America

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Marketing or Sales, Operations

Core offering

Excellicon develops and sells EDA software for timing constraint management in integrated circuit and System-on-Chip (SoC) design. Its platform enables designers to author, compile, certify, formally validate, and manage SDC timing constraints across multi-mode scenarios, and includes tools for clock tree analysis and early RTL feasibility/floorplan planning. The offering targets semiconductor companies seeking to accelerate design closure and optimize power, performance, and area (PPA).

Product overview

Gencellicon is Siemens EDA's timing closure and early design planning suite that offers a comprehensive platform for verifying, generating, and managing SDC (Synopsys Design Constraints) timing constraints. The suite consists of four integrated modules: Constraints Builder for multi-mode timing constraints generation and management; Constraints Certifier for formal validation and timing budget generation; Clock Analyzer for pre-CTS and post-CTS clock tree analysis and guidance file generation; and Chip Planner for RTL feasibility analysis and early floorplan generation. These products collectively enable SoC designers to accelerate design closure, optimize power, performance and area (PPA), and implement a shift-left methodology for more predictable design cycles.

Differentiator

Problem solved

Functional benefit

Products and services

• Gencellicon (formerly Excellicon) Comprehensive timing constraints management platform for SoC designers that enables authoring, compiling, certification, formal validation, and management of multi-mode timing constraints, plus early design planning and clock analysis for accelerated timing closure.
• Constraints Builder Module that generates and manages full-chip, multi-mode timing constraints at the RTL or gate level, with automatic promotion of constraints across hierarchy and clock/data propagation analysis for SoC design teams.
• Constraints Certifier Validation module that performs single-mode and cross-mode timing constraint verification, including formal and SVA-based exception checks, timing budget generation for blocks, and timing equivalency checking for SoC design teams.
• Clock Analyzer Clock analysis and visualization tool providing pre-CTS clocking analysis and debugging, post-CTS clock tree validation, clock propagation analysis, and automatic generation of CTS guidance files including clock exceptions and skew group definitions.
• Chip Planner Early design planning module that performs RTL feasibility analysis to eliminate physical issues early, analyzes optimum partitioning scenarios by goal, estimates PPA at RTL, generates an early floorplan, and produces collaterals for downstream physical implementation tools.

Quantifiable outcome

• Reduction in chip development cycle by orders of magnitude through systematic and correct-by-construction approach

Segments1 record

Ideal customer profiles1 record

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature4 records

Recent moves4 records

Expansion highlights4 records

Broad incumbents

• ANSYS: Major simulation and multiphysics vendor with EDA-adjacent silicon-aware power, thermal, and signal-integrity tools. Comparable as an incumbent in adjacent physical-design analysis used alongside timing closure.
• Siemens EDA (Mentor Graphics): Excellicon's acquirer and the third major EDA vendor, with broad IC design tooling including Questa, Tessent, Aprisa, and PowerPro. Now houses the Gencellicon portfolio within a much wider design platform.
• Keysight Technologies: Major electronic design and test vendor with EDA-adjacent simulation (PathWave) and RF/mixed-signal design tooling. Overlaps the broader EDA simulation and verification space in which Excellicon's customers operate.
• Altair Engineering: Engineering simulation and design optimization vendor with EDA-adjacent electronic system design tooling. Comparable as a broader engineering software incumbent overlapping the design tool ecosystem serving chip and system companies.

Emerging players

• Primarius Technologies: Specialized EDA vendor focused on device-level variability, aging, and statistical timing analysis. Adjacent to Excellicon's domain of advanced timing validation and PPA optimization in SoC designs.
• Zuken: Electronic design tools vendor primarily in PCB and IC packaging design. Comparable as an EDA-adjacent vendor serving hardware design teams with related constraints and system-level design tooling.

Direct peers

• Synopsys: Inventor of the SDC standard and creator of PrimeTime, the dominant gold-standard timing signoff tool used in virtually all SoC design flows. Directly overlaps Excellicon's timing constraint management and validation surface area.
• Real Intent: Specialty EDA vendor focused on signoff-quality timing, formal, and clock-domain crossing verification. Closely overlaps Excellicon's timing constraint correctness and exception verification capabilities.
• Silvaco: EDA and TCAD vendor serving IC design and verification workflows, including digital implementation and signoff-adjacent tools. Comparable as a smaller, specialized EDA peer in IC design.
• Cadence Design Systems: Top-three EDA vendor offering Tempus timing signoff and Innovus implementation within an integrated digital design flow. Directly competes in the timing-closure and SDC management category Excellicon addresses.

Market position

Strengths4 records

Weaknesses4 records

Competitive moat4 records

Key risks6 records

Key highlights6 records

Customer concentration

• Xx.com/excellicon

Revenue estimate

Valuation estimate

Number of profiles

Profiles1 record

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Excellicon