What OpenRoad does

OpenROAD is an open-source digital place-and-route electronic design automation (EDA) tool chain developed at the UC San Diego VLSI CAD Laboratory under Prof. Andrew Kahng and originally funded by DARPA's Electronics Resurgence Initiative through the IDEA program. Its core product targets the cost, expertise, and risk barriers that block hardware designers from accessing advanced semiconductor technology by enabling autonomous, no-human-in-loop RTL-to-GDSII chip layout implementation in approximately 24 hours. The platform addresses academic researchers and students, early-stage semiconductor startups, and government/defense contractors requiring trusted microelectronics.

The technology stack consists of a central OpenROAD engine orchestrated by OpenROAD-flow-scripts and supported by specialized sub-tools: OpenSTA for static timing analysis, OpenRCX for multi-corner parasitic extraction, TritonRoute for detailed routing, RePlace and DREAMPlace (deep-learning placement) for global placement, FastRoute for global routing, TritonCTS for clock tree synthesis, ioPlacer for pin placement, OpenDB for shared data infrastructure, and AutoTuner (Ray-based) for ML-driven hyperparameter optimization. The flow supports multiple open process design kits including SkyWater 130nm, ASAP7 7nm, and IHP SG13G2 130nm, and integrates with downstream controllers such as Efabless OpenLane and DARPA-funded OpenFASoC.

The project's business model is non-commercial: tools are distributed free under permissive BSD-3/MIT/Apache licensing through GitHub and AWS, with monetization gated to adjacent service providers rather than the project itself. Tapeout access is enabled through the Google OpenMPW and Efabless ChipIgnite shuttle programs and IHP's fab-ready shuttle services, while commercial implementation support is offered by Precision Innovations Inc. in partnership with Abacus Semiconductor. The legal entity is the Regents of the University of California, supported by DARPA funding, the newly formed OpenROAD Initiative non-profit foundation (2023), and in-kind contributions from a global academic and industry contributor base spanning the US, Europe, Central America, South America, and Asia.

Name

OpenRoad

Legal name

Regents of the University of California

Website

https://theopenroadproject.org

Company type

Private

Founded year

2018

Operating status

Operating

Headcount range

11–50 employees

Short description

OpenROAD is an open-source RTL-to-GDSII place-and-route EDA tool chain developed at UC San Diego under DARPA funding, enabling autonomous, no-human-in-loop chip layout implementation in 24 hours for academic researchers, semiconductor startups, and government/defense users.

Ownership category

akta.pro rank

Product category

Electronic Design Automation (EDA) Tools

NAICS

Software Publishers (5132)

SIC

Services-Prepackaged Software (7372)

akta.pro primary industry

Platform Engineering & Internal Developer Platforms (IDP) (BPAEAKAC)

Keywords

• Electronic design automation
• Place and route tools
• Semiconductor chip design
• RTL to GDSII flow
• Open source EDA

Headquarters

HQ city

San Diego

HQ country

United States

HQ region

North America

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Infrastructure

Pricing tiers

Distribution channels4 records

Marketing channels6 records

Core offering

OpenROAD is an open-source digital place-and-route (PnR) EDA tool chain that enables autonomous, no-human-in-loop RTL-to-GDSII chip layout implementation within 24 hours. The platform provides a complete flow including synthesis, placement, routing, clock tree synthesis, static timing analysis, and parasitic extraction, supporting multiple process nodes from 130nm to 7nm with permissive BSD-3/MIT/Apache licensing for free commercial and academic use.

Product overview

OpenROAD (Open RObust Application Designer) is an open-source digital place-and-route EDA tool chain developed at UC San Diego VLSI CAD Laboratory as part of DARPA's IDEA program. The core OpenROAD tool enables autonomous, no-human-in-loop RTL-to-GDSII chip layout implementation within 24 hours. The ecosystem consists of the core OpenROAD engine and multiple specialized sub-tools including OpenROAD-flow-scripts for complete RTL-to-GDSII flow, OpenROAD GUI for visualization, OpenSTA for timing analysis, OpenRCX for parasitic extraction, TritonRoute for detailed routing, RePlAce and DREAMPlace for placement, FastRoute for global routing, TritonCTS for clock tree synthesis, and ioPlacer for pin placement. The project supports multiple open PDKs including ASAP7 7nm, SkyWater 130nm, and IHP 130nm. Integration with flow controllers like OpenLane and OpenFASoC enables broader accessibility through programs like Google/Efabless MPW shuttle. OpenROAD leverages ML/AI for optimization (AutoTuner), performance prediction, and is expanding into GenAI for next-generation EDA capabilities.

Differentiator

Problem solved

Functional benefit

Products and services

• OpenROAD Open-source digital place-and-route EDA tool chain enabling autonomous, no-human-in-loop RTL-to-GDSII chip layout implementation in 24 hours. Developed at UC San Diego as part of DARPA IDEA program for academic researchers, semiconductor startups, and government/defense organizations.
• OpenROAD-flow-scripts (ORFS) Complete RTL-to-GDSII flow scripts combining Yosys for synthesis, OpenROAD tools for placement/routing, OpenSTA for timing analysis, and klayout for DRC checking. Provides an end-to-end tapeout-ready flow for academic and commercial chip designers.
• OpenROAD GUI Visualization and debugging interface for layouts, heatmaps (congestion, power, IR drop), DRC viewing, timing path tracing, and schematic display. Enables designers to inspect and debug chip layouts visually.
• OpenSTA (Open Static Timing Analysis) Open-source static timing analysis tool integrated with OpenROAD for timing analysis and optimization throughout the design flow. Used by chip designers to verify timing closure on synthesized and placed designs.
• OpenRCX Parasitic extraction tool supporting multi-corner extraction of R, C values for accurate post-route timing signoff in chip designs.
• TritonRoute Detailed router with DRC-clean output capability for foundry enablement. Developed by Lutong Wang and Bangqi Xu as part of the OpenROAD tool chain.
• RePlAce Global placement tool with timing-driven capabilities for optimal standard cell placement in chip designs.
• DREAMPlace Deep learning-enabled placement optimizer using neural network approaches for placement optimization in chip designs.
• ioPlacer Pin and IO placement functionality for optimal input/output pin placement in chip designs.
• FastRoute Global router for initial routing topology and congestion estimation during placement in chip designs.
• TritonCTS Clock tree synthesis tool for generating balanced clock distributions in chip designs.
• OpenLane Python-based flow controller by Efabless built on OpenROAD, enabling RTL-to-GDSII tapeout through the Google/Efabless MPW shuttle program.
• OpenFASoC DARPA-funded automated SoC and mixed-signal design flow integrating analog and digital components using OpenROAD for physical implementation.
• RTL-MP Hierarchical RTL and dataflow-driven macro placer for better PPA through intelligent macro placement decisions in chip designs.
• OpenDP Placement legalizer replacing NTUPlace binaries in OpenROAD's placement and legalization subflows for chip designs.
• AutoTuner ML-based hyperparameter tuning framework using Ray for cloud-based distributed design exploration and PPA optimization in chip designs.
• METRICS2.1 Open metrics framework for capturing PPA metrics across design search trials, enabling reward function customization for different PPA goals in chip design optimization.
• ASAP7 7nm Predictive PDK Predictive process design kit for 7nm technology node developed at ASU in collaboration with ARM Research, released under BSD-3 license for academic and commercial chip design exploration.
• IHP 130nm Open PDK Public PDK for IHP's 130nm process technology supporting trusted microelectronics development via IHP shuttle services for fab-ready designs.

Quantifiable outcome

• 600+ tapeouts completed using OpenROAD-based flows through Google OpenMPW and Efabless ChipIgnite programs
• +3 more outcomes

Segments3 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

AI capability7 records

Feature7 records

Recent moves7 records

Expansion highlights6 records

Market position

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

• GitHubgithub.com/The-OpenROAD-Project
• LinkedInlinkedin.com/company/openroad-eda
• Xx.com/openroad_eda

Revenue estimate

Valuation estimate

Number of profiles

Profiles3 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about OpenRoad