What IP CORES does

IP Cores, Inc. is a privately held semiconductor intellectual property (IP) vendor headquartered in Palo Alto, California, established circa 2004–2008. The company designs and licenses IP cores for ASIC and FPGA applications, organized around four product pillars: (1) security and cryptography — AES, DES/3DES, SNOW 3G, Kasumi, ZUC, ChaCha20/Poly1305, Simon/Speck, SHA-1/2/3, AES mode cores (GCM, CCM, XTS, CBC, EAX), public-key cores (RSA, ECC), MACsec/IPsec/SSL/TLS security processors, HDCP 2.0, random number generators, and post-quantum cryptography (ML-DSA/ML-KEM); (2) forward error correction — Reed-Solomon (100G Ethernet), BCH, LDPC, and Ethernet cyclic codecs; (3) lossless compression — LZR1, LZR2, and a combined compression/encryption core; and (4) digital signal processing — a family of FFT/IFFT cores from 32 to 4096 points. Products are marketed as the "smallest, fastest, and lowest-cost" choices in their categories, supported by quantitative differentiators such as AES in under 3,000 gates, DES/3DES in 3K gates, ECC1 at 10K gates, BCH1 at 17K gates, and MACsec throughput scaling from 1 Gbps to 400 Gbps via the MSP1/MSP7/MSP10 family. AES1 is FIPS-197 certified, and several cores carry BIS export control classification 5E002.

The company serves semiconductor companies (ASIC/FPGA designers) as its primary buyer segment, with downstream applications in communication equipment manufacturers (WiFi, WiMAX, Zigbee, UWB, Ethernet, LTE/5G) and storage system manufacturers (IEEE P1619 encryption). The go-to-market is sales-led and direct, with quote-based pricing for one-time licenses delivered as Verilog RTL source or netlist (EDIF), accompanied by technical documentation, testbenches, and support. Distribution is entirely direct (phone and email) with no visible reseller, distributor, or channel partner network. Recent commercial activity includes additional shipments of MSP7-32 and MSP7-64 cores announced on 06/10/2025. The firm employs 1–10 people, has no disclosed revenue, and appears to be founder/management-owned and self-funded.

Name

IP CORES

Legal name

IP Cores, Inc.

Website

https://ipcores.com

Company type

Private

Founded year

2004

Operating status

Operating

Headcount range

1–10 employees

Short description

IP Cores, Inc. is a Palo Alto-based semiconductor IP vendor licensing security, compression, forward error correction, and DSP IP cores (HDL source or netlist) to ASIC and FPGA designers across communications, networking, and storage end-markets.

Ownership category

akta.pro rank

Headquarters

HQ city

Palo Alto

HQ country

United States

HQ region

North America

Offices1 record

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations

Revenue model

1. IP Core Licensing: One-time license fees for semiconductor IP cores. Customers license the RTL source code or netlist forms of cryptographic, compression, FEC, and DSP IP cores for integration into their ASIC and FPGA designs.

Go-to-market motion1 record

Distribution channels1 record

Marketing channels2 records

Core offering

IP Cores, Inc. develops and licenses semiconductor intellectual property (IP) cores delivered as synthesizable Verilog RTL source code and netlists for ASIC and FPGA applications. The portfolio specializes in security and cryptography (block/stream ciphers, hash functions, modes of operation, public-key, post-quantum, and protocol processors for MACsec/IPsec/SSL/TLS), and additionally includes lossless compression, forward error correction (LDPC, Reed-Solomon, BCH, Ethernet FEC), and DSP (FFT) cores. Products are marketed as the smallest, fastest, and lowest-cost choices on the market, with standards compliance to NIST FIPS, IEEE 802 series, 3GPP, ETSI SAGE, ITU-T, and IEEE P1619.

Product overview

IP Cores, Inc. offers a comprehensive portfolio of semiconductor intellectual property (IP) cores for ASIC and FPGA applications. The company specializes in security/cryptography cores as well as compression and DSP cores, positioning its products as the smallest, fastest, and lowest-cost choices on the market. The product portfolio includes: (1) Encryption cores - AES, DES/3DES, ChaCha20/Poly1305, Simon/Speck, ZUC, SNOW 3G, Kasumi; (2) Authentication/hash cores - SHA-1/SHA-2, SHA-3, CMAC/XCBC, HMAC; (3) Combined encryption/authentication - GCM, CCM, EAX modes and combos (GCM/CCM/EAX, XTS/GCM, XTS/GCM/CBC, GCM/LRW); (4) Public-key cryptography - RSA2, RSA5X, ECC1, ECC1-PM, ECC7, PQC1 (post-quantum); (5) Security processors - IPsec (ISP1), SSL/TLS (SSL1-AXI), MACsec (MSP1/MSP7/MSP10), HDCP 2.0; (6) Communication standard cores - WiFi (802.11i CCMP/TKIP), WiMAX (802.16e CCM), Zigbee (802.15.4 CCM), UWB MBOA CCM, G.hn CCM; (7) Random number generators - PRNG1 (pseudo-random), TRNG1 (true random); (8) Compression - LZR1 (10 Gbps), LZR2 (low latency), LXP2 (compression + encryption); (9) Forward error correction - CEC1 (Ethernet cyclic), LDPC, RS100 (100G Reed-Solomon), BCH1/BCH10; (10) DSP - FFT cores (32-4096 points), Viterbi detector. The cores are delivered as synthesizable Verilog RTL with optional netlist forms.

Differentiator

Problem solved

Functional benefit

Products and services

• AES IP Core (AES1) Ultra-compact AES (Rijndael) IP core implementing FIPS-197 certified encryption with 128-bit and 256-bit keys. Self-contained core with less than 3,000 ASIC gates, supporting ECB, CFB, CBC, OFB and CTR modes; key expander included, no external memory required. For ASIC/FPGA designers requiring certified hardware AES.
• DES/3DES IP Core (DES1) Ultracompact DES and 3DES implementation per NIST FIPS 46-3, available in just 3K ASIC gates. For ASIC/FPGA designers needing compact legacy block-cipher encryption.
• AES Key Wrap IP Core (AKW1) AES key wrap and unwrap implementation per NIST specification using both 128 and 256 Key Encryption Keys (KEK). For ASIC/FPGA designers implementing key management in hardware.
• Pseudo Random Number Generator (PRNG1) Cryptographically secure pseudo-random number generator per NIST SP800-90 publication. For ASIC/FPGA designs requiring hardware RNG.
• True Random Number Generator (TRNG1) True random number generator suitable for ASIC and FPGA families, providing cryptographically secure output per SP800-90. For hardware security modules and key generation.
• SNOW 3G IP Core (SNOW3G1) Stream cipher implementing keystream generation for 3GPP LTE algorithms UEA2 and UIA2 per ETSI SAGE specification. For ASIC/FPGA designs in 3GPP LTE equipment.
• Kasumi Block Cipher (KSM1) Block cipher implementation per ETSI SAGE specification and 3GPP publication TS 35.202. For 3GPP mobile communication ASIC/FPGA designs.
• SHA1/SHA2 IP Core Cryptographic hash implementations including SHA-1 core and SHA-2 with SHA2-256 and SHA2-512 variants. For ASIC/FPGA hardware cryptographic designs.
• Generic CCM Core (CCM1) Full flow-through implementation of CCM (CTR+CBC) encryption and decryption for generic CCM applications. For ASIC/FPGA designers implementing authenticated encryption.
• Combo GCM/CCM/EAX Core (GCE1-MP) Rijndael encoding/decoding implementation supporting GCM, CCM, CCM*, and EAX' encryption/authentication modes per NIST AES standard. For ASIC/FPGA designers needing flexible authenticated encryption.
• ZUC Cipher Core (ZUC1) Implementation of the ZUC cipher for Chinese 3GPP mobile market with EIA3/EEA3 mode support. For ASIC/FPGA designs in Chinese 3GPP mobile equipment.
• ChaCha20/Poly1305 Core Stream cipher implementation for authenticated encryption using the ChaCha20 and Poly1305 algorithms. For ASIC/FPGA designs requiring modern authenticated encryption.
• Simon/Speck Cores Lightweight block cipher implementations for resource-constrained environments. For ASIC/FPGA designs in IoT and embedded security.
• SHA3 IP Core SHA-3 cryptographic hash cores (SHA3-224, SHA3-256, SHA3-384, SHA3-512) implementing Keccak algorithms per FIPS 202, with optional HMAC, KMAC, and XOF (SHAKE) functions. For ASIC/FPGA hardware cryptographic designs.
• GCM IP Core Family (GCM1/GCM2/GCM3/GCM10) High-speed AES/GCM implementation for IEEE 802.1AE (MACSec) standards. GCM1 compact core (less than 13K gates, 1-6 Gbps), GCM2 scalable (5-40 Gbps, up to 70-100 Gbps), GCM3 with 256-bit keys, GCM10 delivering 120+ Gbps. For ASIC/FPGA LAN security designs.
• XTS IP Core Family (XTS2/XTS3) High-throughput XEX-AES cores supporting IEEE P1619 standard. XTS2 for 128-bit keys, XTS3 for both 128 and 256-bit keys. For storage encryption ASIC/FPGA designs.
• Combo XTS/GCM Core (GXM2/GXM3) Combined AES-XTS and AES-GCM mode implementation supporting IEEE P1619 and 802.1ae standards. GXM2 for 128-bit keys, GXM3 for 256-bit AES keys. For storage and network security ASIC/FPGA designs.
• Combo XTS/GCM/CBC Core (GXC3) Combined XTS, GCM, and legacy CBC mode encryption for storage and network storage applications. For ASIC/FPGA storage controller designs.
• LRW-AES Core High-speed LRW-AES (Liskov-Rivest-Wagner) encryption and decryption implementation. For storage security ASIC/FPGA designs.
• Combo GCM/LRW Core (GLM1/GLM2) Combined high-speed LRW and GCM mode encryption/decryption implementations. For storage security ASIC/FPGA designs.
• RC4/ARC4 Core High-performance RC4/aRC4 stream cipher implementation. For ASIC/FPGA legacy stream-cipher security designs.
• AES-CMAC/XCBC Core (CMAC1) Flow-through implementation of CMAC and XCBC cryptographic hash functions. For ASIC/FPGA message authentication designs.
• AES-CCM/CMAC Core (CCM2) Flow-through AES-CCM and CMAC algorithm implementation. For ASIC/FPGA authenticated encryption designs.
• WiMAX 802.16e CCM Core Full CCM encryption/decryption according to IEEE 802.16e standard for WiMAX applications. For WiMAX ASIC/FPGA designs.
• WiFi 802.11i CCM Core (CCMP) Full CTR+CBC (CCMP) encryption and decryption per IEEE 802.11i (WPA, WPA2) WLAN standard using less than 9,000 gates. For WiFi ASIC/FPGA designs.
• WiFi CCMP/TKIP/RC4 Core (WPA3) Flow-through implementation of all WiFi cipher suites including CCMP, TKIP, and RC4 with encryption context lookup option. For ASIC/FPGA WiFi security designs.
• Zigbee CCM Core AES-CCM encryption for IEEE 802.15.4 standard used as the base for ZigBee specification. For Zigbee ASIC/FPGA designs.
• IEEE 802.15.3 CCM Core Full CCM encryption and decryption according to IEEE 802.15.3 standard. For ASIC/FPGA designs in IEEE 802.15.3 short-range wireless.
• UWB MBOA CCM Core Full CCM implementation according to Multi-Band OFDM (MBOA) UWB standard. For ASIC/FPGA designs in MBOA UWB.
• G.hn AES-CCM Core Full CCM encryption per ITU G.9960 standard for home network applications. For ASIC/FPGA designs in G.hn home networking.
• WAPI/SMS4 Processor (WPI1) Chinese WAPI standard implementation using SMS4 cipher. For ASIC/FPGA designs targeting Chinese WAPI wireless security market.
• Post-Quantum Cryptography Core (PQC1) Post-quantum cryptography accelerator supporting ML-DSA and ML-KEM algorithms for hardware. For ASIC/FPGA designs requiring post-quantum security.
• RSA2 Compact RSA Core RSA exponentiation implementation enabling low-power operation for battery-powered devices. For ASIC/FPGA designs needing compact public-key cryptography.
• ECC1 Compact ECC Core Elliptic curve cryptography core implementing point multiplication and point verification, extremely compact at 10K gates. For ASIC/FPGA designs needing compact public-key cryptography.
• RSA5X RSA/Elliptic Combo Combo RSA/ECC cryptography accelerator supporting both public-key algorithms. For ASIC/FPGA designs needing flexible public-key cryptography.
• ECC7 High-Speed ECC High-speed elliptic curve cryptography technology using the mathematics of elliptic curves. For ASIC/FPGA designs requiring high-throughput public-key operations.
• IPsec Processor (ISP1) IPsec security processor implementing IPv4/IPv6 packet support, ESP/AH protocols, AES-CBC/TripleDES encryption, HMAC-SHA1/AES-XCBC authentication. Peak throughput of 12.8 bits per clock (7.7 Gbps at 600 MHz for AES-128). For ASIC/FPGA network security designs.
• IPsec/SSL/TLS Processor Combined IPsec and SSL/TLS acceleration processor. For ASIC/FPGA designs requiring combined network security protocol acceleration.
• SSL/TLS Processor with AXI (SSL1-AXI) SSL/TLS processor with AXI bus interface for control (AXI3/AXI4 slave) and data transfer (AXI3/AXI4 master). Throughput of 6-8 bits per clock (600-800 Mbps at 100 MHz). Optional RSA and ECC public-key engines. For ASIC/FPGA designs with AXI-based SoC integration.
• MACsec Processor (MSP1) MACsec processor implementing IEEE 802.1AE LAN security standard using AES-GCM encryption and authentication with header parsing/formatting. For ASIC/FPGA LAN security designs.
• MACsec Processor (MSP7) High-performance MACsec processor designed for high data rates with complete line-rate packet processing and no per-packet CPU intervention. Available in MSP7-32 and MSP7-64 variants (announced additional shipments 06/10/2025). For ASIC/FPGA high-throughput LAN designs.
• MACsec Processor for MoreThanIP MAC (MSP5-M) MACsec processor designed for close integration with MoreThanIP Anyspeed MAC. For ASIC/FPGA designs targeting pairings with MoreThanIP Anyspeed MAC products.
• 400 Gbps MACsec Processor (MSP10-512/256) High-throughput MACsec processor supporting 400 Gbps data rates for LAN security per IEEE 802.1AE. For high-end ASIC designs for 400G networking.
• HDCP 2.0 Suite Complete HDCP 2.0 implementation for content protection. For ASIC/FPGA designs in HDMI/DisplayPort content-protected interfaces.
• 10 Gbps Compression Core (LZR1) Lossless compression IP core for short data units (frames) up to 4096 bytes. For ASIC/FPGA designers requiring hardware lossless compression.
• Low Latency Compression Core (LZR2) Very low-latency compression core with sustained 8 bits per clock throughput. For ASIC/FPGA designs requiring low-latency lossless compression.
• Compression + Encryption Core (LXP2) Lossless compression/decompression combined with AES-XTS encryption/decryption on data blocks. For ASIC/FPGA designs in storage controllers requiring combined compression and storage encryption.
• 100G Ethernet Reed-Solomon Codec (RS100) 100G Ethernet Reed-Solomon codec for Clause 91 (IEEE 802.3bj) supporting 25/50/100Gbps Ethernet. For ASIC/FPGA designs in 100G Ethernet optical/backplane.
• Ethernet Cyclic Codec (CEC1) Codec implementing Forward Error Correction cyclic code (2112,2080) for IEEE 802.3ap (10G Backplane Ethernet) and IEEE 802.3ba (40/100 Gbps) standards. For ASIC/FPGA Ethernet FEC designs.
• LDPC Codec Low-density parity-checking codec for forward error correction applications. For ASIC/FPGA designs requiring high-performance LDPC FEC.
• BCH1 Compact BCH Codec Parameterizable compact BCH codec for lower-performance error correction applications prioritizing small size over performance (17K gates max for n=511 t=16 configuration). For ASIC/FPGA designs needing compact BCH FEC.
• BCH10 Very Low Latency BCH Codec Very low-latency BCH codec for high-performance error correction ASIC applications with high k (~500) and small t (3-5), prioritizing latency over size. For ASIC designs needing low-latency BCH FEC.
• Multi-Stream FFT4T 128-point complex FFT and IFFT implementation over multiple data streams, running at clock frequency four times higher than input sampling frequency. For ASIC/FPGA DSP designs.
• 512/1024 Point FFT Core High-performance FFT/IFFT cores supporting 512 and 1024 point transforms. For ASIC/FPGA DSP designs.
• 64 Point FFT Core High-performance FFT/IFFT core supporting 64 point transforms. For ASIC/FPGA DSP designs.
• 32-4096 Point FFT Core (FFT4096) Flexible FFT/IFFT core supporting 32, 64, 128, 256, 512, 1024, 2048, and 4096 point transforms for ADSL, powerline, and other communication applications. For ASIC/FPGA DSP designs.
• FFT1-32-512 Core 32 to 512 point FFT and IFFT implementation running at clock frequency four times higher than input sampling frequency. For ASIC/FPGA DSP designs.

Quantifiable outcome

• AES core as small as less than 3,000 gates
• +4 more outcomes

Segments3 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature13 records

Scale indicators1 record

Recent moves6 records

Expansion highlights5 records

Direct peers

• VeriSilicon: VeriSilicon is a silicon platform-as-a-service and IP licensing company that designs and licenses processor, DSP, security, and interface IP cores to ASIC/SoC customers — closely comparable business model and customer base to IP Cores.
• CAST, Inc. CAST sells a broad catalog of semiconductor IP cores including AES, DES, SHA, public-key cryptography, compression, and interface cores — a near-direct overlap with IP Cores' product portfolio and B2B ASIC/FPGA customer motion.
• Rambus: Rambus is a direct competitor in security/cryptography semiconductor IP, offering crypto cores, MACsec engines, and protocol security IP for ASICs and FPGAs targeting the same networking and data-center customer base as IP Cores.
• Secure-IC: Secure-IC specializes in embedded cybersecurity IP cores and post-quantum cryptography accelerators for SoCs, competing with IP Cores' PQC1, RSA/ECC, and protocol-security portfolio.
• Barco Silex (Barco): Barco Silex is a long-standing European supplier of cryptography and security IP cores (AES, public-key, IPsec, MACsec) for ASIC and FPGA designs, directly competing with IP Cores in the security IP niche.
• Menta S.A.S: Menta licenses embedded FPGA (eFPGA) IP cores that customers integrate into ASICs — a comparable independent semiconductor IP licensing business selling reusable silicon IP to the same ASIC/SoC customer base.
• Silicon Creations: Silicon Creations licenses high-performance analog and mixed-signal IP (PLLs, SerDes, I/O) to ASIC/FPGA customers; while its primary focus differs, it is a comparable independent IP-licensing business model selling cores into the same ASIC design teams.

Broad incumbents

• Cadence Design Systems: Cadence offers a broad semiconductor IP portfolio including Tensilica DSP, security IP, and interface solutions, competing with IP Cores across multiple product lines and bundling IP into full EDA-to-silicon flows.
• Synopsys: Synopsys' DesignWare IP portfolio includes security, processor, interface, and DSP IP widely used by ASIC designers. As the largest EDA+IP incumbent, it competes with IP Cores across nearly every protocol and offers bundled, pre-verified subsystems.
• Silvaco: Silvaco offers EDA tools together with semiconductor IP including interconnect, memory compilers, and standard cells, providing broader EDA-platform competition to standalone IP vendors like IP Cores.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat4 records

Key risks5 records

Key highlights6 records

Customer concentration

Compliance2 records

Revenue estimate

Valuation estimate

Number of profiles

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about IP CORES