Entasys

What Entasys does

Entasys Design Inc. is a Korean-headquartered electronic design automation (EDA) software company founded in 2003 that delivers point tools for system-on-chip (SoC) design planning, RTL floorplanning, constraint management, and transistor-level critical path analysis. The portfolio is anchored by NavisPro, an RTL hierarchical floorplanning suite that combines Navis-CM (constraint validation, clock and low-power design intent analysis) and Navis-FP (power-and-timing aware floorplanning with PadOptima), and TRASTA, a transistor-level critical path analyzer with built-in STA, pattern-matching for sub-circuit identification, CCG cell characterization, and SPICE netlist generation with back-annotated parasitics. Supporting tools - TimingInspector, PathInspector, PadLVS, DesignAdvisor, LibWiz, Navis-ES, Navis-DI, and Pillar-DP-SVP - extend coverage across pre-RTL silicon virtual prototyping, post-layout timing debug, pad-ring verification, and library consistency across LEF, DEF, GDS-II, Liberty, and Verilog HDL formats. The intended users are SoC designers in fabless design houses, foundries, and integrated device manufacturers seeking to reduce design iterations, prevent late-stage IC implementation problems, and improve first-silicon success rates.

The company operates a B2B enterprise software model based on per-seat and project licensing for EDA tools, supplemented by maintenance and technical support contracts. Go-to-market combines direct enterprise field sales from a Seoul headquarters and a Sunnyvale, California US office (established 2008-2009) with a regional distributor channel - most notably Gemfour in Shanghai for China, and historically IVIS in Japan and Ornan Tech in Korea (both signed January 2011). Marketing is heavily event-driven, anchored on the annual Design Automation Conference (DAC), where Entasys exhibited consistently from 2008 through 2020. End customers are concentrated among Korean and Asian semiconductor and electronics companies, including Samsung Electronics (the largest customer), LG Electronics, SK Hynix, Spreadtrum Communications, and Dongbu HiTek. No public pricing, customer-count, headcount, or revenue disclosure is available.

Since June 25, 2021, Entasys has operated as a wholly-owned subsidiary of Primarius Technologies Co., Ltd., following an M&A transaction intended to strengthen semiconductor-market competitiveness through combined financial resources and technology synergies. Leadership overlap between the two entities is significant: Lianfeng Yang, Ph.D. serves as CEO of Entasys and President/COO of Primarius, and Bob Xu sits on both boards. The company has been recognized through Korean government certifications (KOITA R&D Center, 2010; INNO-BIZ, 2015) and third-party validation by Japan's STARC for its optimal PAD configuration flow (2011).

Name

Entasys

Legal name

Entasys Design Inc.

Website

https://entasys.com

Company type

Private

Founded year

2003

Operating status

Operating

Headcount range

1–10 employees

Short description

Entasys Design Inc. is a Korean-headquartered EDA software vendor founded in 2003, providing SoC design planning, RTL floorplanning, and transistor-level critical path analysis tools such as NavisPro and TRASTA to major semiconductor and electronics companies including Samsung, LG, and SK Hynix.

Ownership category

akta.pro rank

Product category

Electronic Design Automation (EDA) Software

NAICS

Computer Systems Design and Related Services (5415)

SIC

Services-Computer Programming Services (7371)

akta.pro primary industry

EDA Software Platforms (Digital Implementation, Verification & Signoff) (HDAHAFAA)

akta.pro secondary industry

System-Level, Multi-Physics & Package/PCB Co-Design (EDA) (HDAHAFAD)

Keywords

• Electronic design automation
• SoC design planning
• RTL floorplanning software
• Timing analysis tools
• Semiconductor verification software

Headquarters

HQ city

Seoul

HQ country

South Korea

HQ region

Asia

Offices2 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Marketing or Sales, Operations, Infrastructure

Revenue model

1. EDA Software Licenses and Support: B2B enterprise software sales of EDA tools (NavisPro, TRASTA, and related products) for SoC design planning and verification. Likely includes software licenses, maintenance, and technical support contracts.
2. Distribution and Reseller Revenue: Revenue through distributor network including Gemfour (Shanghai) Technology Co., Ltd. for China market and other regional distributors.

Go-to-market motion3 records

Distribution channels4 records

Marketing channels3 records

Core offering

Entasys Design Inc. provides electronic design automation (EDA) software for System-on-Chip (SoC) design planning, verification, and debugging. Its product suite spans RTL-level floorplanning (NavisPro), transistor-level critical path analysis (TRASTA), power pad optimization (PadOptima), timing debugging (TimingInspector, PathInspector), and ESL-level silicon virtual prototyping (Pillar-DP-SVP), targeting semiconductor design teams to achieve first-silicon success with reduced design iterations.

Product overview

Entasys Design Inc. is an EDA (Electronic Design Automation) company founded in 2003, providing semiconductor design planning and verification solutions. The product portfolio consists of multiple integrated tools organized around design planning and design inspection. NavisPro is the flagship RTL design planning solution comprising Navis-CM (constraint validation) and Navis-FP (hierarchical floorplanning). TRASTA handles transistor-level critical path analysis. The company also offers PadOptima for optimal power pad configuration, TimingInspector and PathInspector for timing debugging, PadLVS for pad ring verification, LibWiz for library analysis, and DesignAdvisor for design constraints management. Earlier products include Ventus/Navis-ES for power and area estimation, and Pillar-DP®-SVP for ESL-level silicon virtual prototyping. All tools are designed for SoC engineers to achieve first-silicon success with minimized design turnaround time.

Differentiator

Problem solved

Functional benefit

Brands

• NavisPro: RTL Design Planning Solution including chip estimation, design constraints validation, and floorplanning.
• Navis-CM
• Navis-FP
• TRASTA
• Navis-ES
• Navis-DI
• PadOptima
• DesignAdvisor
• PathInspector
• TimingInspector
• PadLVS
• LibWiz
• Pillar-DP-SVP

Products and services

• NavisPro Comprehensive RTL design planning solution for billion-gate SoC designs. Power and timing aware, predicts and prevents IC implementation problems across the early design flow for semiconductor design teams.
• TRASTA Transistor Level Critical Path Analyzer that automatically identifies critical paths and enables designers to analyze selected critical paths with highest precision using built-in STA engine and SPICE netlist generation, targeting SoC timing closure teams.
• Pillar-DP-SVP Comprehensive pre-RTL Silicon Virtual Prototyping solution including micro-architecture level power and area estimation, hierarchical floorplanning, package aware IO pad configuration, and automatic power network prototyping.
• PadOptima Optimal Power Pad Configuration tool that finds optimum number and location of power pads to minimize design iteration, preventing excessive voltage drop and SSO noise with IO and core power pad optimization.
• PathInspector Physical aware timing debugging solution with interactive design exploration that identifies critical paths and enables analysis with highest precision for timing closure.
• TimingInspector Physical Aware Timing Debugging Solution providing efficient timing ECO covering all design constraints and corners, with timing path analysis, clock tree analysis, and I/O path analysis.
• PadLVS Pad Ring Verification tool that supplements existing LVS verification flow with pad ring connectivity check and power/ground net connection verification.
• DesignAdvisor Design analysis and exploration solution for SoC design constraints management including clock structure analysis, power domain analysis, and clock network analysis.
• LibWiz Library analysis and generation tool providing consistency check between different library formats (Liberty, Verilog HDL, LEF, GDSII, Spice) for standard cell, I/O cell, and IP cell.
• Navis-ES Power and Area Estimation tool for system-on-chip design at micro-architecture level with built-in analytic power estimator and interactive floorplanner.
• Navis Early SoC Design Planning Solution providing power and timing aware pre-RTL design planning with power/area estimation, optimal pad configuration, and initial floorplanning.
• Ventus Power and area estimation tool for SoC design at micro-architecture level using built-in static power estimator and interactive floorplanner.

Quantifiable outcome

• Minimizes unnecessary design iterations and achieves faster time-to-market for SoC products
• +2 more outcomes

Named customers5 records

Segments1 record

Ideal customer profiles1 record

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration2 records

Feature9 records

Partnerships

Six partnerships are on record, tiered core and minor.

• Primarius Technologies Co., Ltd.coreStrategic or Co-development Partner · 25 June 2021M&A transaction closed on June 25, 2021. Entasys became a wholly-owned subsidiary of Primarius Technologies. The combination strengthens competitiveness in semiconductor market with better financial support and technology synergies.
• IVISminorChannel Partner/ Reseller/ Distributor · 10 January 2011Distributor agreement signed January 2011 for distribution of Entasys products. IVIS is a technology distributor based in Japan (i-vis.co.jp).
• Ornan TechminorChannel Partner/ Reseller/ Distributor · 10 January 2011Distributor agreement signed January 2011 for distribution of Entasys products. Ornan Tech is a technology distributor (ornantech.com).
• Si2 (Silicon Integration Initiative)minorStrategic or Co-development PartnerIndustry consortium of leading semiconductor, electronic systems and EDA companies focused on improving productivity and reducing cost in creating and producing integrated silicon systems. Entasys participates in Low-Power Coalition (LPC) with over 15 member companies.
• COSAR (Consortium of Semiconductor Advanced Research)minorStrategic or Co-development PartnerKorea government consortium launched in 1986 focusing on System on Chip engine design and process development. Entasys participates in tasks including system IC for Smart-Car, system IC for Telemetrics, and GPS/Galileo complex system IC.
• Gemfour (Shanghai) Technology Co., Ltd.minorChannel Partner/ Reseller/ DistributorDistributor for China market covering Shanghai region. Contact: [email protected], Tel: +86 21 6628 7138.

Scale indicators8 records

Recent moves7 records

Expansion highlights6 records

Regional players

• Zuken: EDA vendor with strong presence in Japan and Asia, focused on PCB and package-aware design. Comparable to Entasys in chip-package co-design through Pillar-DP-SVP and is geographically complementary in the Japan market where Entasys has had historical distributor relationships.

Broad incumbents

• Synopsys: Largest EDA company with a full-stack digital implementation, verification, and signoff platform (Fusion Compiler, PrimeTime, VCS). Competes with Entasys across RTL floorplanning, constraint validation, and timing analysis as part of a much broader portfolio.
• Cadence Design Systems: Major EDA incumbent with digital implementation, signoff, and IP tools (Innovus, Genus, Tempus, Voltus). Cadence is the most directly comparable broad incumbent to Entasys given leadership overlap (Lianfeng Yang, Bob Xu both ex-Cadence).
• Siemens EDA (formerly Mentor Graphics): Broad EDA incumbent offering Calibre, Tessent, and verification tools. Competes with Entasys in physical verification, design-for-test, and integrated design planning categories as part of a portfolio that includes IC design and PCB co-design.
• ANSYS: Major multi-physics and simulation vendor with EDA-adjacent offerings (RedHawk, Totem) for power, IR-drop, and SI analysis. Directly competes with Entasys's IR-drop, SSN noise, and power integrity capabilities.

Direct peers

• Real Intent: Specialized EDA vendor focused on signoff verification including CDC, Lint, and timing analysis. Competes head-to-head with Entasys's DesignAdvisor and TimingInspector offerings in clock/constraint verification and post-layout timing debugging.
• Primarius Technologies: Parent company of Entasys since the 2021 M&A. Provides EDA tools for device modeling, characterization, and circuit simulation; the combination with Entasys creates product overlap in front-end design planning and verification.

Emerging players

• Concept Engineering: Provider of visualization and debugging tools for electronic system design, including RTL and Gate-level schematic generation. Overlaps with Entasys in design analysis and physical-aware timing debugging adjacent workflows.
• Agnisys: Specialized EDA vendor for specification-driven IP and SoC design automation, including register and sequence generation. Adjacent to Entasys in spec-driven design planning and constraint management.
• Blue Pearl Software: Smaller EDA vendor providing clock domain crossing (CDC) analysis, Lint, and design checks for FPGAs and ASICs. Overlaps with Entasys in constraint validation and design analysis workflows.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights6 records

Customer concentration

• LinkedInlinkedin.com/company/entasys-design

Revenue estimate

Valuation estimate

Number of profiles

Profiles4 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Entasys