RaaS

What RaaS does

RaaS (Research Association for Advanced Systems / 先端システム技術研究組合) is a Tokyo-based, METI-approved cooperative research association (研究組合) established on August 17, 2020 to commercialize advanced semiconductor design and 3D integration capabilities as a service. Its technical stack is built around three pillars: a Silicon Compiler that enables software-like chip design, an Agile Design Platform targeting 10x development efficiency through open architecture, and 3D Integration Technology using low-temperature hybrid Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) bonding on 7nm CMOS processes for a stated 10x energy efficiency improvement. Supporting research includes aluminum nitride (AlN) films with high thermal conductivity for 3D chiplets (in collaboration with Ryukoku University) and surface-activated room-temperature bonding (led by advisor Professor Suga).

The consortium operates a membership-based model with full members (University of Tokyo, Hitachi, MIRISE Technologies, SCREEN Holdings, DAIKIN, FUJIFILM, Panasonic Connect, ADVANTEST, RIKEN, Toppan) and associate members (Toyota Motor, DENSO, EBARA, EBARA FIELD TECH), chaired by Professor Tadahiro Kuroda (Director, Systems Design Lab (d.lab), University of Tokyo). RaaS has no externally disclosed revenue, pricing, or headcount; its funding is structurally tied to member contributions and Japanese government subsidies, most notably the 2021 selection into METI's Post-5G Information and Communications System Infrastructure Enhancement R&D Project executed via NEDO. Go-to-market is sales-led and relationship-driven: members join through direct consortium agreements and the organization disseminates progress through academic publications, government forums, and industry venues (SEMICON Japan, VLSI Symposium, IEEE EPS Japan, JEITA committees). Target use cases span AI accelerators, autonomous driving, smart factory, Post-5G communications, and energy-conscious computing, but no external commercial customers or production-volume deployments are evidenced.

Name

RaaS

Legal name

先端システム技術研究組合

Website

https://raas-cip.org

Company type

Private

Founded year

2020

Operating status

Operating

Short description

RaaS is a Tokyo-based, METI-approved Japanese research consortium (established 2020) that provides advanced semiconductor design and 3D integration technology as a service to a closed membership of major Japanese corporates and research institutions, targeting 10x development and 10x energy efficiency gains.

Ownership category

akta.pro rank

Product category

Semiconductor Research Services

NAICS

Scientific Research and Development Services (5417), Computer Systems Design and Related Services (54151)

SIC

Semiconductors & Related Devices (3674), Services-Commercial Physical & Biological Research (8731)

akta.pro primary industry

Custom & Application-Specific ASIC Design Services (HDAHABAJ)

akta.pro secondary industries

Assembly & Packaging Services (Wirebond/Flip-Chip/FCBGA) (HDAHADAA), Package Substrates & Interposers (ABF/BT, Silicon/Glass) (HDAHADAE)

Keywords

• Advanced semiconductor research
• Chip design platform
• 3D integration technology
• Research as a service
• Post-5G semiconductors

Headquarters

HQ city

Tokyo

HQ country

Japan

HQ region

Asia

Offices1 record

Markets served

GTM type

B2B

Offering type

Services

Cost components

Personnel, Technology or R&D, Operations, Infrastructure, Marketing or Sales, Others

Revenue model

1. Research as a Service (RaaS): RaaS provides access to advanced semiconductor technology as a service through a membership-based research consortium model. Users gain access to chip design platforms and 3D integration capabilities for specialized chip development. Revenue is generated through consortium membership fees and government-funded research projects.

Go-to-market motion1 record

Distribution channels1 record

Marketing channels7 records

Core offering

RaaS (Research Association for Advanced Systems) delivers advanced semiconductor technology as a service (Research as a Service) through a membership-based research consortium. Its core offerings include the Agile Design Platform for rapid prototyping of specialized chips, the Silicon Compiler that enables software-like chip design, and 3D Integration Technology using advanced CMOS processes (including 7nm) and low-temperature hybrid bonding (WoW/CoW). The service targets industrial members seeking to design specialized chips for AI, Post-5G, smart factory, and autonomous driving applications without bearing the full cost of in-house semiconductor R&D.

Product overview

RaaS (Research Association for Advanced Systems) is a research consortium that provides cutting-edge semiconductor technology as a service (Research as a Service). The organization operates as a platform consortium with interconnected components: the Agile Design Platform enables rapid chip prototyping with 10x development efficiency; the Silicon Compiler enables software-like chip development methodology; and 3D Integration Technology achieves 10x energy efficiency through advanced CMOS and 3D stacking. The Next-Generation Advanced Semiconductor Design Platform is a collaborative R&D initiative involving University of Tokyo, ADVANTEST, Toppan, Hitachi, MIRISE Technologies, and RIKEN for democratizing chip design. Users can create specialized chips the same way they write software to achieve digital transformation.

Differentiator

Problem solved

Functional benefit

Products and services

• Agile Design Platform An agile development platform that enables quick-turn prototyping of specialized chips, targeting a 10-fold improvement in development efficiency through open architecture deployment. Allows users to design chips in a manner similar to writing software.
• Silicon Compiler A disruptive compiler-based technology that enables designing chips as one writes software, reducing hardware development costs and risks while expanding the population of hardware designers. It is the foundational innovation underpinning the Agile Design Platform.
• 3D Integration Technology An advanced 3D integration technology offering that includes Wafer-on-Wafer (WoW) and Chip-on-Wafer (CoW) bonding using low-temperature hybrid bonding, enabling chips manufactured with advanced 7nm CMOS processes to be stacked in the same package for a targeted 10x energy efficiency improvement.

Quantifiable outcome

• 10x development efficiency improvement through agile design platform and open architecture
• +2 more outcomes

Segments2 records

Ideal customer profiles2 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature6 records

Partnerships

Seven partnerships are on record, tiered core and minor.

• Ryukoku University (龍谷大学)coreStrategic or Co-development PartnerCollaborative research partnership on advanced 3D chiplet technology. Joint research on AlN films with high thermal conductivity for advanced 3D chiplets, presented at VLSI Symposium 2024 and Japan Society of Applied Physics.
• NEDO (New Energy and Industrial Technology Development Organization)coreStrategic or Co-development PartnerGovernment-backed research partnership for Post-5G semiconductor manufacturing technology development. RaaS selected by METI for NEDO-subsidized project on advanced semiconductor manufacturing technology.
• Tokyo University - Systems Design Lab (d.lab)coreTechnology or IntegrationCore technology partner providing systems design research capabilities. Led by Professor Tadahiro Kuroda, Director of Systems Design Lab at Graduate School of Engineering, University of Tokyo.
• IEEE EPS Japan ChapterminorStrategic or Co-development PartnerIndustry collaboration through presentations at IEEE EPS Japan Evening Meeting on Post-5G project efforts and advanced packaging technology.
• JEITA (Japan Electronics and Information Technology Industries Association)minorStrategic or Co-development PartnerIndustry association participation in advanced packaging committees and scene-oriented implementation technology subcommittee meetings.
• EDA VendorscoreTechnology or IntegrationPartnership with EDA (Electronic Design Automation) vendors for chip design platform infrastructure as part of the consortium ecosystem.
• LSI FoundriescoreTechnology or IntegrationPartnership with LSI foundries for chip prototyping and manufacturing using advanced CMOS processes including 7nm technology node.

Scale indicators3 records

Recent moves7 records

Expansion highlights4 records

Direct peers

• Imec: Belgium-based world-leading semiconductor R&D consortium with a multi-member, government-partnered research model. Directly comparable to RaaS as a nonprofit research hub pooling industry/academic talent to advance process, packaging, and design technologies.
• Semiconductor Research Corporation (SRC): US-based semiconductor research consortium funding university research aligned with member company roadmaps. Same consortium-of-members business model as RaaS, focused on advancing semiconductor design, materials, and manufacturing science.
• CEA-Leti: France's CEA-Leti is a major applied-research institute focused on semiconductor, 3D integration, and advanced packaging. Same model as RaaS — government-funded institute partnering with industrial members on next-generation chip technology.
• ITRI (Industrial Technology Research Institute): Taiwan's flagship applied-research organization with deep semiconductor R&D and pilot-line capabilities. Comparable to RaaS in mission (industry-led semiconductor research consortium) and adjacent to Japan's industrial-policy-driven RaaS model.

Broad incumbents

• Arm Holdings: Dominant processor IP provider whose accessible IP model embodies 'democratization of chip design.' Comparable to RaaS's stated mission of lowering barriers to specialized chip creation for industrial use cases.
• Siemens EDA (Mentor Graphics): Third major EDA incumbent with strong position in physical verification, IC packaging, and 3D-IC design. RaaS's 3D integration technology targets workflows Siemens EDA serves today.
• Synopsys: Largest EDA vendor with leading digital design, verification, and silicon IP portfolios. Competes with RaaS's design platform vision and provides the design infrastructure that RaaS members currently rely on.
• Cadence Design Systems: Global EDA leader whose tools and IP ecosystem cover chip design, verification, and packaging. RaaS's Silicon Compiler and Agile Design Platform compete conceptually against Cadence's design automation stack for advanced-node and 3D-IC workflows.

Emerging players

• Eliyan: Emerging chiplet interconnect specialist focused on die-to-die PHY/UCIe solutions for multi-die designs. Operates in the same 3D/2.5D chiplet integration space as RaaS's WoW/CoW bonding and 3D stack work.
• Achronix Semiconductor: FPGA and eFPGA IP company leveraging advanced packaging and chiplet architectures. Comparable to RaaS as a specialized chip design platform player targeting differentiated performance/efficiency outcomes.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights6 records

Customer concentration

Revenue estimate

Valuation estimate

Number of profiles

Profiles2 records

Funding overview

Funding rounds

Investors

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M&A

Investments

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Frequently asked questions about RaaS