What Chip Interfaces does

Chip Interfaces ApS is a privately held Danish semiconductor IP company headquartered in Lyngby, Denmark, that designs and licenses high-performance digital IP cores for chip-to-chip interface standards. The portfolio spans a broad set of protocols including JESD204 (B/C/D/E), Interlaken, CPRI/eCPRI, UCIe D2D, UALink (TL/DL/PCS), Ultra Ethernet (UEC v1.0), IEEE 802.3 Ethernet MAC/PCS scaling to 1.6T, MACsec, DIFI, O-RAN, and MIPI I3C/RFFE. Implementations are silicon-agnostic and target both ASIC and FPGA flows, with products verified via UVM regression methodologies and validated through multiple tape-outs across different process nodes and fabs. Chip Interfaces notably delivered the industry's first commercially available JESD204D IP core, taped out with a Tier 1 semiconductor company in October 2024, and has built co-verified stacks with leading SerDes/PHY providers including Cadence, EXTOLL, and Silicon Creations.

The company's revenue model is built on one-time or perpetual IP core licenses delivered via direct enterprise sales, supplemented by engineering support services for IP integration and tape-out. Pricing is quote-based with multi-year contract cadences; there are no public price lists or self-service channels. Go-to-market relies on a datasheet request funnel, a technical blog, whitepapers, newsletter, and LinkedIn presence, with named target customers including tier-1 semiconductor companies, ASIC designers, and SoC makers across AI/HPC, telecom/RAN, aerospace/defense, and satellite communications. Leadership consists of CEO Anne Voss Winther and Head of R&D Jørgen Carstensen, with an organization sized at 11–50 employees.

Recent milestones (2024–2026) include interoperability testing with Cadence's 112G Long-Reach SerDes PHY (January 2025), Eridan ASIC collaboration via EXTOLL on GlobalFoundries 22FDX (August 2025), MIPI I3C Plugfest participation with Soliton and Prodigy Technovations (September 2025), Silicon Creations interoperability validation for JESD204B/C, Interlaken, and CPRI (December 2025), entry into the YorChip Physical AI Chiplet Ecosystem (February 2026), and the launch of the industry's first integrated UCIe IP solution for GlobalFoundries FDX with EXTOLL (May 2026).

Name

Chip Interfaces

Legal name

Chip Interfaces ApS

Website

https://www.chipinterfaces.com

Company type

Private

Operating status

Operating

Headcount range

11–50 employees

Short description

Denmark-based Chip Interfaces designs digital IP cores for high-speed chip-to-chip interfaces including JESD204, Interlaken, UCIe, UALink, and Ultra Ethernet. It licenses IP to tier-1 semiconductor companies, ASIC designers, and SoC makers across AI/HPC, telecom, aerospace, and satellite communications.

Ownership category

akta.pro rank

Headquarters

HQ city

Copenhagen

HQ country

Denmark

HQ region

Europe

Offices1 record

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales, Infrastructure

Revenue model

1. IP Core Licensing: Chip Interfaces licenses digital IP cores to semiconductor companies and ASIC designers. The licensing model provides access to silicon-proven IP cores with deliverables including documentation, simulation environment, test cases, programming register specifications, and timing constraints. The company offers direct support from engineers who designed the IP cores throughout the implementation process.
2. Engineering Support Services: Direct support from Chip Interfaces Engineers for IP integration and bring-up. Support includes PHY integration packages and assistance with tape-out processes.

Pricing tiers

Go-to-market motion1 record

Distribution channels2 records

Marketing channels5 records

Core offering

Chip Interfaces licenses silicon-agnostic digital IP cores for high-speed chip-to-chip interface protocols, including JESD204, Interlaken, UCIe, UALink, Ultra Ethernet, CPRI/eCPRI, O-RAN, MIPI I3C/RFFE, and DIFI. These IP cores are sold to semiconductor companies, ASIC designers, and SoC makers for ASIC and FPGA implementations. The company also offers associated verification IP, hardware platforms for evaluation, and direct engineering support throughout the IP integration and tape-out process.

Product overview

Chip Interfaces provides digital IP cores for high-performance chip-to-chip interface standards. The product portfolio centers on interconnect protocols including JESD204 (B/C/D/E) for data converters, Interlaken for chip-to-chip communications, CPRI/eCPRI for radio fronthaul, and UCIe for chiplet interconnects. Additional products include UALink for AI/HPC accelerator fabrics, Ultra Ethernet and standard Ethernet MAC/PCS for networking, MACsec for security, DiFi for satellite communications, O-RAN for open radio access, and MIPI I3C/RFFE for sensor and RF front-end interfaces. The company offers these as standalone IP cores with associated verification IP, hardware platforms, and integration support, targeting ASIC and FPGA implementations across multiple process nodes.

Differentiator

Problem solved

Functional benefit

Products and services

• JESD204 IP (B/C/D/E) Digital IP cores for the JEDEC JESD204 high-speed serial interface standard for data converters, supporting versions B, C, D, and E with line rates up to 116 Gbps, featuring RS FEC for error correction and deterministic latency. Targeted at semiconductor companies, ASIC designers, and SoC makers building data converter interfaces.
• Interlaken IP Scalable chip-to-chip protocol IP supporting up to 2.6 Tbps bandwidth with 48 lanes at up to 56 Gbps. Includes Retransmit and RS FEC extensions for error recovery. Designed for ASIC and FPGA implementations across AI, HPC, and data center applications.
• CPRI 6.1 IP Silicon-agnostic Common Public Radio Interface IP supporting line rates up to 12.16 Gbps with dynamic mapping and RS-FEC. Targeted at 5G radio base station and fronthaul equipment developers.
• CPRI 7.0 IP High-speed serial interface IP for radio equipment supporting line rates up to 24.33 Gbps with 64B/66B PCS. Targeted at 5G and 4G radio base station equipment manufacturers.
• eCPRI IP Packet-based fronthaul interface IP for 5G networks supporting 10G/25G Ethernet with dynamic configuration for multi-mode radio. Targeted at 5G mobile network equipment developers and open RAN solution providers.
• UCIe D2D Adapter Die-to-die adapter layer for UCIe chiplet interconnect supporting 32 Gbps per pin, CRC/Retry, and multi-protocol multiplexing including PCIe, CXL, and streaming protocols. Targeted at chiplet designers and SoC integrators.
• UCIe Protocol Layer AXI-S AXI5-Stream protocol layer for UCIe D2D stacks enabling streaming protocol communication across chiplets. Targeted at chiplet designers using AXI-Stream interfaces.
• UA Link TL Transaction Layer implementation for UALink_200 specification supporting 200-800 Gbps per link with atomic operations and authentication. Targeted at AI and HPC accelerator interconnect designers.
• UA Link DL Data Link Layer implementation for UALink_200 specification with flit packing and link level replay. Targeted at AI and HPC accelerator interconnect designers.
• UA Link PCS Physical Coding Sublayer for UALink_200 supporting 100G-800G with RS-FEC and deterministic flit alignment. Targeted at AI and HPC accelerator interconnect designers.
• Ultra Ethernet MAC & PCS Complete silicon-agnostic implementation of Ultra Ethernet Transport link layer compliant with UEC Specification v1.0, supporting 100G to 800G configurations with LLR and CBFC. Targeted at HPC and data center networking ASIC designers.
• Ethernet MAC 100G-1.6T IEEE 802.3 compliant Media Access Control IP for 100 Gbps to 1.6 Tbps Ethernet operations. Targeted at networking ASIC designers and data center equipment manufacturers.
• Ethernet PCS 100G-1.6T Physical Coding Sublayer IP for Ethernet 100G-1.6T with RS-FEC and multiple link configurations. Targeted at networking ASIC designers and data center equipment manufacturers.
• High Speed MACsec Engine IEEE 802.1AE-2018 compliant Layer 2 security IP for 100G-1.6T Ethernet with AES-GCM encryption. Targeted at networking ASIC designers needing hardware-accelerated encryption.
• DiFi IP Digital IF Interoperability implementation of IEEE-ISTO Std 4900-2021 for satellite communications supporting up to 100 Gbps. Targeted at satellite communication and ground station gateway ASIC developers.
• O-RAN Front Haul Interface O-RAN WG4 7.2x interface implementation for O-DU and O-RU products supporting 25 Gbps. Targeted at open RAN equipment developers and 5G mobile network operators' vendors.
• MIPI I3C Controller IP MIPI I3C v1.1.1 compliant IP supporting SDR, HDR modes up to 100 Mbps with multi-controller and target roles. Targeted at sensor interface and mobile/embedded SoC designers.
• MIPI RFFE Master IP MIPI RFFE v3.1 controller for RF front-end components supporting up to 15 slaves and 52 MHz clock. Targeted at mobile RF front-end and smartphone chipset designers.
• MIPI RFFE Slave IP MIPI RFFE v3.1 slave implementation for RF front-end control with configurable registers. Targeted at RF front-end component manufacturers and mobile device chipset designers.
• JESD204 Verification IP UVM-based verification IP for JESD204 compliance testing and validation. Targeted at ASIC verification engineers working on JESD204 implementations.
• JESD204 Hardware Platform Hardware platform for testing and demonstrating JESD204 IP functionality. Targeted at ASIC and FPGA design teams evaluating JESD204 integration.
• Interlaken Hardware Platform Hardware platform built on VCU 118 for demonstrating Interlaken IP with packet generators and checkers. Targeted at ASIC and FPGA design teams evaluating Interlaken integration.
• Integrated UCIe D2D Adapter & PHY Combined UCIe D2D Adapter with EXTOLL PHY providing a complete UCIe solution from 4-16 Gbps per lane. Targeted at chiplet designers seeking a pre-integrated, co-verified UCIe solution for GlobalFoundries FDX technology.

Quantifiable outcome

• Up to 2.6 Tbps total bandwidth per IP instance with Interlaken
• +3 more outcomes

Named customers2 records

Segments4 records

Ideal customer profiles1 record

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature7 records

Partnerships

Four partnerships are on record, tiered minor and core.

• YorChipminorStrategic or Co-development Partner · 17 February 2026YorChip launched the Physical AI Chiplet Ecosystem (PACE) with multiple semiconductor IP partners. The ecosystem includes Chip Interfaces along with Dolphin Technology, QuickLogic, Everspin Technologies, and Blumind, co-developing interoperable and re-useable Chiplets to address high development costs and long time-to-market that have hindered wider Chiplet adoption.
• EXTOLLcoreTechnology or IntegrationEXTOLL is a leading supplier of high speed and ultra low power SerDes and Chiplet connectivity. Together with Chip Interfaces, EXTOLL provides high-performance, fully standard compliant JESD204 Highspeed Interconnects. Both companies are working together to bring JESD204 connectivity to the emerging chiplet interface standard UCIe. EXTOLL's PHYs and Chip Interface's Controllers are available as pre-integrated, easy to integrate solutions for highly demanding customers.
• CadencecoreTechnology or IntegrationCadence is a global leader in electronic design automation (EDA) and silicon intellectual property (IP) solutions, delivering industry leading IP for advanced interface standards. Cadence and Chip Interfaces work together to provide comprehensive IP solutions for next-generation designs, including successful interoperability testing of Interlaken IP with Cadence's 112G Long-Reach SerDes PHY.
• Silicon CreationscoreTechnology or IntegrationSilicon Creations is a leading silicon IP developer providing world-class SerDes IP proven in high volume mass production. Chip Interfaces and Silicon Creations closely collaborate integrating Chip Interfaces IPs with Silicon Creations SerDes to provide comprehensive end-to-end solutions. Successful interoperability validated for JESD204B/C, Interlaken, and CPRI with Silicon Creations' Multi-Protocol SerDes PMA(s).

Scale indicators4 records

Expansion highlights5 records

Broad incumbents

• Synopsys: Synopsys' DesignWare IP portfolio is the broadest interface IP offering in the market (including UCIe, PCIe, Ethernet, DDR, MIPI), competing directly with Chip Interfaces on every protocol the Danish company sells. Synopsys is a BROAD_INCUMBENT due to its vastly larger portfolio and scale.
• Cadence Design Systems:

Market position

Strengths5 records

Weaknesses5 records

Competitive moat4 records

Customer concentration

• LinkedInlinkedin.com/company/chip-interfaces

Revenue estimate

Valuation estimate

Number of profiles

Profiles2 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Chip Interfaces