What Zero ASIC does

Zero ASIC is a U.S. semiconductor company headquartered in Cambridge, Massachusetts, founded in 2008 as Adapteva and rebranded under its current name in 2020 to pursue a mission of democratizing silicon through composable chiplets and open-source design automation. The company operates with a small team of approximately 11 engineers and became profitable in late 2025, with funding secured for a five-year runway. Its product portfolio centers on an eFabric active 3D silicon interposer platform that integrates standardized eBrick and ioBrick chiplets, supported by an open-standard eFPGA IP family (Platypus), an autonomous chip package compiler (PackageCompiler), and an ecosystem of open-source EDA tools including SiliconCompiler, Logik, Wildebeest, Switchboard, and the UMI chiplet interconnect protocol. Technical differentiators include sub-0.1 pJ/bit chiplet communication energy efficiency, 512 Gb/s/mm on-fabric bisection bandwidth, and a roadmap targeting 24-hour RTL-to-GDS compilation cycles versus traditional 2-3 year ASIC development timelines.

The platform targets enterprise and government buyers in high-reliability sectors — aerospace, defense, automotive, healthcare, communications, and industrial — that need custom silicon efficiency but cannot absorb the $100M+ NRE and multi-year timelines of traditional ASIC development, as well as long-lifecycle FPGA-based systems facing obsolescence and counterfeiting risks. Zero ASIC generates revenue through a mix of IP licensing (Platypus eFPGA cores), chiplet catalog sales (eBrick building blocks), per-project licensing for its FPGA Architect platform, custom ASIC design services, and software subscriptions for its cloud-based design and emulation platform. Its go-to-market combines direct enterprise sales, a product-led self-serve web-based emulation experience, and a deep open-source developer community anchored on GitHub. The company is a member of the UCIe Consortium, participates in DARPA-funded programs (including the UT-Austin-led $850M Next Generation Microelectronics program), and was named as a participant in the DoD Phase 2 chip initiative alongside Microsoft, Qualcomm, GlobalFoundries, and BAE Systems.

Name

Zero ASIC

Legal name

Zero ASIC Corporation

Website

https://zeroasic.com

Company type

Private

Founded year

2008

Operating status

Operating

Headcount range

11–50 employees

Short description

Zero ASIC is a Cambridge, Massachusetts semiconductor company building a composable chiplet platform — featuring the eFabric active 3D interposer, Platypus open-standard eFPGA IP, PackageCompiler, and a suite of open-source EDA tools — serving aerospace, defense, automotive, healthcare, and industrial customers needing custom long-lifecycle silicon.

Ownership category

akta.pro rank

Product category

Semiconductor Design Automation and Chiplet IP

NAICS

Custom Computer Programming Services (541511), Computer Systems Design and Related Services (54151)

SIC

Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH)

akta.pro secondary industries

EDA Software Platforms (Digital Implementation, Verification & Signoff) (HDAHAFAA), Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF), IP Enablement, Characterization & Porting Services (HDAHAFAI), AI Hardware IP & Chiplet/Packaging for Accelerators (EDA/IP, advanced packaging) (HDAAAAAL)

Keywords

• Chiplet platform
• FPGA IP cores
• Silicon design automation
• Open-source EDA tools
• Semiconductor IP licensing

Headquarters

HQ city

Lexington

HQ country

United States

HQ region

North America

Offices1 record

Markets served

GTM type

B2B

Offering type

Software

Cost components

Technology or R&D, Personnel, Infrastructure, Marketing or Sales, Operations

Revenue model

1. Chiplet IP Licensing and ASIC Design Services: Zero ASIC generates revenue through licensing of its commercial eFPGA IP cores (Platypus Z1015 12nm and others), chiplet design services, and custom ASIC development. The FPGA Architect platform is offered on a per-project basis. Early access programs allow select customers to evaluate products before general availability.
2. Software Platform Subscriptions: The company offers paid account tiers for its cloud-based design and emulation platform, with private repositories and advanced features available through subscription. Pricing and payment terms are available at zeroasic.com/pricing, with monthly and annual billing options.
3. eBrick Chiplet Catalog Sales: Pre-fabricated composable chiplets (processors, FPGAs, SRAM, ML accelerators) sold as off-the-shelf building blocks for system composition, reducing per-design NRE costs for customers.

Pricing tiers

Go-to-market motion3 records

Distribution channels3 records

Marketing channels5 records

Core offering

Zero ASIC provides a composable chiplet platform that combines standardized eBrick and ioBrick chiplets with the eFabric active 3D silicon interposer, enabling System-in-Package assembly at sub-0.1 pJ/bit energy efficiency. The company licenses its open-standard Platypus eFPGA IP cores (available in multiple process nodes including 12nm) and sells pre-fabricated chiplet building blocks. It also offers a suite of open-source EDA tools (SiliconCompiler, Logik, Wildebeest, PackageCompiler, Switchboard) that automate RTL-to-GDS and chip package design, accessible via a cloud-based browser platform.

Product overview

Zero ASIC is a semiconductor startup offering a platform-plus-tools architecture for democratizing silicon through composable chiplets and open-source design automation. The core platform consists of the eFabric active 3D silicon interposer for chiplet integration, paired with the Platypus family of open-standard eFPGA IP cores (available in multiple sizes and process nodes including 12nm), and PackageCompiler for autonomous chip package design. The tool ecosystem includes Logik (RTL-to-bitstream FPGA toolchain), SiliconCompiler (ASIC compilation framework), Wildebeest (open-source FPGA synthesis tool), Switchboard (high-performance RTL/FPGA/Python/C++ co-simulation), and UMI (chiplet interconnect protocol). A cloud-based emulation platform enables users to compose and emulate custom chiplet-based SoC designs directly in the browser.

Differentiator

Problem solved

Functional benefit

Brands

• Platypus: World's first open-standard eFPGA IP product family, including Z1000, Z1012, Z1015, and other variants with open architecture and bitstream formats.
• Wildebeest
• Logik
• PackageCompiler
• eFabric
• eBrick
• Switchboard
• SiliconCompiler
• UMI
• Zaui

Products and services

• Platypus eFPGA Family of open-standard embedded FPGA (eFPGA) IP cores that address FPGA obsolescence and vendor lock-in by providing standardized, open-architecture programmable logic. Includes multiple cores (z1000, z1002, z1010, z1012, z1015, z1060, z1062) with varying LUT sizes, resource counts, and process nodes including 12nm. Licensed to enterprise customers in aerospace, defense, healthcare, automotive, and industrial markets.
• PackageCompiler World's first fully autonomous chip package compiler that treats package design as a software compilation problem. Takes YAML/JSON design specifications and autonomously generates manufacturing-ready package layouts including KiCad and Gerber outputs, with a unified 3D data model, integrated DRC/LVS validation, and browser-based 3D design viewer. Targeted at chip designers and packaging engineers.
• Wildebeest World's highest-performance open-source FPGA synthesis tool. Achieves Quality of Results (QoR) comparable to proprietary tools through circuit-size-adaptive optimization algorithms and advanced speculative synthesis commands, outperforming both proprietary and open-source alternatives on benchmark designs. Distributed as open-source via GitHub for FPGA developers and researchers.
• Logik Lightweight open-source RTL-to-bitstream FPGA toolchain powered by SiliconCompiler. Provides Python-driven single-step execution that sequences Yosys for synthesis, VPR for place and route, and FASM for bitstream generation. Integrates OpenSTA for timing analysis and supports multiple FPGA architectures through VPR-compatible models. Targeted at FPGA developers.
• SiliconCompiler Open-source circuit design automation framework for orchestrating RTL-to-GDS compilation flows. Sequences multiple EDA tools, provides metrics reporting, supports build automation, and is used in multiple successful ASIC tapeouts. Available as both open source and subscription-based API access. Co-developed by Andreas Olofsson with collaborators Noah Moroze and William Ransohoff.
• Switchboard Open-source high-performance communication framework for communication between RTL simulations, FPGA emulations, Python, and C++. Uses shared memory queues providing up to 1 GB/s bandwidth and 200 ns latency, powering Zero ASIC's cloud-based chiplet digital twin emulator. Provides Python bindings (PySbTx, PySbRx) and a C++ interface.
• eFabric Active 3D Silicon Interposer Platform Active 3D silicon interposer platform that improves die-to-die communication efficiency and composability. Supports integration of ultra-critical processing blocks using 3D-attached eBrick chiplets and 2D-attached UCIe-based ioBrick chiplets. Achieves sub-0.1 pJ/bit chiplet communication efficiency, 512 Gb/s/mm on-fabric bisection bandwidth, and billions of unique System-in-Package assembly options. Targeted at chiplet-based system designers.
• Chiplet Emulation Platform Cloud-based FPGA emulation platform powered by Switchboard, enabling users to compose custom chiplet-based SoCs by dragging iobricks and ebricks onto an eFabric canvas, then emulating the design on FPGA hardware with a Yocto-generated Linux terminal. Accessible via web browser at emulation.zeroasic.com.
• eBrick Chiplets Series of 2mm x 2mm interoperable 3D chiplets including a quad-core RISC-V Linux-capable dual-issue processor, 5K LUT embedded FPGA, 3 MB SRAM, and 3 TOPS machine learning accelerator. Sold as off-the-shelf building blocks for system composition to reduce per-design NRE costs.
• UCIe Interface IP Low-complexity prototype implementation of the UCIe (Universal Chiplet Interconnect Express) standard specification v1.1, supporting raw mode, 16b wide, up to 8GT/s, tightly coupled mode. Designed in GlobalFoundries GF12LP process node using open-source EDA tools.
• FPGA Architect Platform Per-project enterprise platform offered to customers using Zero ASIC's eFPGA technology. Customers engage directly with the sales team for licensing of Platypus eFPGA IP cores, chiplet design services, and FPGA Architect platform access on a per-project basis with multi-year contract options.

Quantifiable outcome

• Wildebeest achieves 2312 LUTs on z1060 (vs. vendor tool's 2870) and 3593 LUTs on z1010 (vs. ice40 Yosys's 4378) for picorv32 CPU benchmark
• +4 more outcomes

Named customers2 records

Segments3 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

Yes

API docs

API detail

Core technology

AI maturity

App detail

Integration11 records

Feature9 records

Partnerships

Five partnerships are on record, tiered minor, core and flagship.

• Latch-Up Conference CommunityminorStrategic or Co-development Partner · 19 April 2024Zero ASIC presented the Switchboard open-source communication framework and the Universal Memory Interface (UMI) protocol at Latch-Up 2024, an open-source circuit design conference.
• UCIe ConsortiumcoreStrategic or Co-development Partner · 17 October 2023Zero ASIC joined the UCIe (Universal Chiplet Interconnect Express) industry consortium in December 2022 to promote open chiplet standards and reduce barriers to chiplet design and manufacturing. The company contributes to the UCIe standard body and has implemented a low-complexity UCIe v1.1 interface prototype in GF12LP process.
• Open Compute Project (OCP) / Chiplet Economy CentercoreStrategic or Co-development Partner · 17 October 2023Zero ASIC presented at the Open Compute Platform Summit (Open Chiplet Economy Center) in October 2023 in San Jose, CA, demonstrating its platform for composable chiplet-based SoC design within the OCP ecosystem.
• SiliconCompiler/Open-Source Community ContributorscoreStrategic or Co-development Partner · 15 December 2022The SiliconCompiler project (launched 2021) was co-developed by Andreas Olofsson with collaborators Noah Moroze and William Ransohoff. The broader open-source EDA community contributes to projects including Yosys, VPR, Verilator, Xyce, Icarus, Slang, and others that are integrated into Zero ASIC's toolchain.
• Microsoft and Qualcomm (DoD Chip Initiative Phase 2)flagshipStrategic or Co-development Partner · 23 November 2021Zero ASIC was named as a participant in the DoD's second-phase chip initiative led by Microsoft and Qualcomm Technologies, alongside Ansys, Applied Materials, BAE Systems, Cadence, GlobalFoundries, Intel Federal, Raytheon, Siemens EDA, and others. The initiative leverages U.S. microelectronics capabilities while securing the technology supply chain.

Scale indicators8 records

Recent moves7 records

Expansion highlights6 records

Direct peers

• QuickLogic: QuickLogic is a direct eFPGA IP competitor, offering Australis eFPGA IP cores targeting similar aerospace/defense, IoT, and edge AI customers. Both companies pursue embedded FPGA IP licensing as a core business, though QuickLogic is more established in the market.
• Flex Logix: Flex Logix develops eFPGA and reconfigurable acceleration IP, directly competing with Zero ASIC's Platypus family in the eFPGA IP market. Both target semiconductor companies needing embedded programmable logic without vendor lock-in.
• Achronix Semiconductor: Achronix provides eFPGA IP and standalone FPGAs targeting similar high-performance networking, compute acceleration, and defense applications. Competes directly on eFPGA IP licensing to ASIC/SoC designers.

Broad incumbents

• Synopsys: Synopsys is the dominant EDA platform incumbent with a broad portfolio spanning synthesis, place-and-route, IP cores, and verification - directly overlapping Zero ASIC's SiliconCompiler, Logik, Wildebeest, and IP offerings, though as part of a much larger closed-source suite.
• Cadence Design Systems: Cadence is a top-three EDA incumbent offering digital implementation, verification, and silicon IP. Competes with Zero ASIC's toolchain across the chip design flow and is a DoD chip initiative partner alongside Zero ASIC.
• Siemens EDA (Siemens Digital Industries): Siemens EDA (formerly Mentor Graphics) is a top-three EDA platform provider competing with Zero ASIC's open-source toolchain. Also a DoD chip initiative partner, overlapping with Zero ASIC's defense and aerospace customer base.
• Rambus: Rambus licenses semiconductor IP including chiplet interface IP and memory interface protocols. Compares to Zero ASIC's UMI protocol and UCIe interface IP though Rambus is much larger and targets HBM/memory rather than chiplet interconnect broadly.

Emerging players

• Efabless: Efabless is an open-source chip design platform enabling community-driven ASIC creation via cloud tools and shared MPW shuttle runs. Shares Zero ASIC's mission of democratizing silicon design but focuses on open-source ASIC tapeouts rather than chiplets and eFPGA.
• ChipFoundry: ChipFoundry is an emerging open-source silicon platform providing cloud-based chip design and fabrication services. Shares Zero ASIC's open-source silicon democratization mission with a more software-platform-only approach and no proprietary IP.

Others

• GlobalFoundries: GlobalFoundries is the foundry partner for Zero ASIC's 12nm Platypus eFPGA cores (GF12LP/LPP) and UCIe interface implementation. Functions as both an enabler and indirect ecosystem peer as it advances its own FDX/12LP platform for chiplet designs.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

• GitHubgithub.com/zeroasiccorp
• LinkedInlinkedin.com/company/zeroasic
• Xx.com/adapteva
• Facebookfacebook.com/Adapteva

Revenue estimate

Valuation estimate

Number of profiles

Profiles5 records

Funding overview

Funding rounds3 records

Investors2 records

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Zero ASIC