What Imperas does

Imperas is a privately held EDA and processor verification technology company founded in 2005 and headquartered in Palo Alto, California, with 11–50 employees. The company specializes in reference model-based verification for custom RISC-V processors, targeting semiconductor companies and processor designers who need to verify complex, configurable RISC-V implementations — including custom ISA extensions, interrupts, Debug Mode, privilege modes, virtual memory, multi-hart, multi-issue, and out-of-order pipelines — before tape-out. Its core technology is the ImperasFPM (Fast Processor Model), an industry-proven, configurable, and extensible RISC-V reference model that is paired with a proprietary pipeline synchronization technology capable of handling asynchronous events that frequently generate verification bugs.

The company's flagship product is ImperasDV, a front-end design verification solution that performs lock-step continuous compare co-simulation between the processor's RTL and the ImperasFPM reference model. As each instruction retires, the architectural state of the two is compared and any mismatch is reported immediately at the point of failure, eliminating wasted simulation cycles. ImperasDV connects to the processor under test through the open RISC-V Verification Interface (RVVI), integrates with the Synopsys verification toolchain (VCS for logic simulation, Verdi for debug, HAPS for prototyping, and ZeBu for emulation), and can be driven from SystemVerilog/UVM testbenches. A complementary product, ImperasTS, provides test suites for complex and configurable RISC-V ISA extension sets, and the same ImperasFPM is reused for both hardware verification and software development.

Imperas monetizes through one-time enterprise licenses of ImperasDV and distributes exclusively through Synopsys as part of Synopsys's verification portfolio, marketed under the ImperasDV brand by Synopsys's global enterprise sales force. The company has been acquired by Synopsys, making its technology a core part of Synopsys's RISC-V processor verification offerings and effectively channeling Imperas's reference-model IP to every major semiconductor design account in Synopsys's installed base. Marketing is conducted through Synopsys's product pages, white papers, webinars, and technical articles.

Name

Imperas

Legal name

Imperas

Website

https://imperas.com

Company type

Private

Founded year

2005

Operating status

Operating

Headcount range

11–50 employees

Short description

Imperas provides reference model-based RISC-V processor verification solutions for semiconductor companies designing custom RISC-V cores. Its ImperasDV platform uses lock-step continuous compare co-simulation to verify processor correctness before tape-out, distributed exclusively through Synopsys's global verification portfolio.

Ownership category

akta.pro rank

Product category

Semiconductor Verification Software

NAICS

Computer Systems Design Services (541512)

akta.pro primary industry

Verification IP (VIP) & Protocol Compliance Suites (HDAHAFAG)

Keywords

• RISC-V processor verification
• Semiconductor EDA tools
• RTL verification software
• Processor reference models
• Hardware design verification

Headquarters

HQ city

Palo Alto

HQ country

United States

HQ region

North America

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Marketing or Sales, Operations, Infrastructure

Revenue model

1. ImperasDV Verification Software: Enterprise EDA verification software sold to semiconductor companies and RISC-V processor designers. Revenue generated through licensing of ImperasDV verification solution as part of Synopsys's verification portfolio.

Go-to-market motion1 record

Distribution channels1 record

Marketing channels2 records

Core offering

Imperas provides front-end design verification solutions for custom RISC-V processors and instruction-set architectures, using a reference-model-based lock-step continuous compare methodology. The flagship product ImperasDV is distributed exclusively through Synopsys as part of their verification portfolio, paired with the proprietary ImperasFPM reference model and ImperasTS test suites for comprehensive functional verification of RISC-V designs.

Product overview

Imperas provides processor verification solutions centered around its ImperasDV product, a front-end design verification solution for RISC-V processors. ImperasDV uses the ImperasFPM (Fast Processor Model) as a reference model and implements a lock-step continuous compare co-simulation methodology between RTL and the reference model. The solution integrates with Synopsys VCS for RTL simulation, Verdi for debug, and Synopsys HAV solutions (HAPS and ZeBu) for emulation and prototyping. ImperasTS provides complementary test suites for RISC-V ISA extension sets.

Differentiator

Problem solved

Functional benefit

Brands

• ImperasFPM: RISC-V Fast Processor Model used as reference model for processor verification in the ImperasDV solution

Products and services

• ImperasDV

Segments1 record

Ideal customer profiles1 record

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration7 records

Feature5 records

Partnerships

One partnership is on record.

• SynopsyscoreOEM/ Whitelabel/ Licensing PartnerImperas technology is distributed as ImperasDV through Synopsys's verification portfolio. Synopsys integrates Imperas's reference model technology into their EDA toolchain including VCS simulation, Verdi debug platform, and hardware-assisted verification solutions (HAPS and ZeBu). Imperas was acquired by Synopsys, making it a core part of Synopsys's processor verification offerings.

Recent moves5 records

Expansion highlights4 records

Regional players

• BlueChek (Arteris): Arteris provides SoC IP and verification IP adjacent to processor design, with growing RISC-V ecosystem engagement. Listed as a comparable adjacent vendor serving overlapping semiconductor customers, though not a direct RISC-V verification competitor.

Direct peers

• Breker Verification Systems: Specialty vendor of portable stimulus and verification IP for processor and SoC designs, including RISC-V targets. Directly comparable as a focused verification IP/tools company addressing similar processor verification challenges.
• SiFive: Leading commercial RISC-V processor IP provider whose customers also need verification flows for custom RISC-V cores. Comparable because SiFive's customer base overlaps with Imperas's buyer profile (RISC-V processor designers).

Broad incumbents

• Cadence Design Systems: Major EDA competitor to Synopsys with its own RISC-V verification flow (Palladium emulation, Xcelium simulation). Comparable as a competing supplier of processor verification tools to the same semiconductor customer base.
• Siemens EDA (Mentor Graphics): Third major EDA incumbent with Questa simulation and Catapult HLS, pursuing RISC-V verification capabilities. Comparable as a competing EDA vendor targeting the same processor verification use cases.
• Synopsys: Global EDA leader and Imperas's parent company/acquirer. Sells VCS, Verdi, HAPS, and ZeBu and now bundles ImperasDV as its RISC-V verification solution — directly comparable because Imperas's product is integrated into Synopsys's verification stack.

Emerging players

• Codasip: RISC-V processor IP vendor that also offers Studio toolchain for custom RISC-V core development and verification. Comparable because it sells into the same custom-RISC-V design workflow with both IP and verification-adjacent tooling.
• OpenHW Group: Open-source hardware organization producing RISC-V cores (e.g., CORE-V) and verification IP including CV32E40P and associated test/verification infrastructure. Comparable as a source of open-source RISC-V verification alternatives to ImperasDV.
• Antmicro: RISC-V tooling and services company that builds open-source verification, simulation, and CI infrastructure (e.g., Renode, cocotb-based flows) for RISC-V designs. Comparable as an alternative verification tooling provider in the same ecosystem.

Others

• RISC-V International: Standards body governing the RISC-V ISA, including the RVVI verification interface that ImperasDV uses. Comparable as the ecosystem shaper whose specifications Imperas must track and whose compliance frameworks partially substitute for commercial verification IP.

Market position

Strengths4 records

Weaknesses4 records

Competitive moat3 records

Key risks6 records

Key highlights5 records

Customer concentration

• Xx.com/imperassoftware
• LinkedInlinkedin.com/company/imperas

Revenue estimate

Valuation estimate

Number of profiles

Profiles3 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Imperas