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RISC-V International

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uuid000fxeo

Namestring
RISC-V International
Legal namestring
RISC-V International Association
Websiteurl
riscv.org
Company typeenum
Private
Founded yearint
2015
Descriptiontext

RISC-V International Association is a non-profit standards organization founded in 2015 and headquartered in Zurich, Switzerland, following a 2020 relocation from the United States to escape licensing restrictions imposed by Intel and ARM. The organization maintains and ratifies the RISC-V instruction set architecture (ISA), an open, royalty-free standard providing a common platform for processor design across data center, edge AI, automotive, aerospace, IoT/embedded, and HPC workloads. Recent ratified milestones include the RVA23 profile and the RISC-V Server Platform Specification 1.0 (both 2024), which establish standardized baselines for application processors and server-class boot systems respectively.

The organization generates revenue primarily through membership fees (Premier, Strategic, and Community Organization tiers) across a membership base exceeding 4,500 organizations worldwide, supplemented by training and certification programs including the RISC-V Fundamentals + Foundational Associate (RVFA) exam bundle. Its go-to-market is community-led: technical working groups ratify specifications, regional events (RISC-V Summits, World RISC-V Days) drive adoption, and software ecosystem commitments from Canonical (Ubuntu 26.04 LTS RVA23 support), Red Hat, and PyTorch upstreaming anchor developer mindshare. Notable strategic members include Nvidia, Microsoft, Google, Huawei, Tencent, and Alibaba, and the organization operates under the Linux Foundation umbrella with a small staff of 11-50 employees. The core product is the ratified RISC-V specification library; monetization derives from the standardization, certification, and governance work required to maintain an open standard used in over 1 billion cores shipped annually (NVIDIA alone, 2024).

Short descriptiontext

RISC-V International is a non-profit standards body that develops and ratifies the open, royalty-free RISC-V instruction set architecture, serving over 4,500 member organizations across semiconductor, data center, AI, automotive, and aerospace markets.

Operating statusenum
Operating
Ownership categoryenum
Headcount rangeband
11–50
akta.pro rankint
HeadquartersSan Francisco, United States
HQ citystring
San Francisco
HQ countrystring
United States
HQ regionstring
North America
Markets served

Serves global market

Offices1 record

Each record includes

City, Country, Type, Description, Source

Keyword5 values
open instruction set architecture, processor design standards, hardware ISA specifications, RISC-V technology, open standard computing
NAICS code2 codes
  • Business Associations813910
  • Professional, Scientific, and Technical Services541
SIC code1 code
  • Services-Membership Organizations8600
Product category
Open Instruction Set Architecture Standards
GTM motion1 record

Each record includes

Type, Description, Source

Revenue model2 records
1Membership Fees
TypeSubscription Recurring
Description

RISC-V International generates revenue through membership fees from companies and individuals. Membership options include Premier, Strategic, and Community Organization tiers. Companies join to actively influence the development of the open, royalty-free instruction set architecture.

riscv.org
2Training and Certification
TypeProfessional Services
Description

RISC-V International offers training programs and certification exams, including the RISC-V Fundamentals + Foundational Associate (RVFA) exam bundle designed for computer engineers and programmers.

riscv.org
Marketing channels7 records

Each record includes

Title, Type, Stage, Description, Source

Distribution channels1 record

Each record includes

Title, Type, Scope, Target buyer, Description, Source

Cost components5 values
Personnel, Technology or R&D, Marketing or Sales, Operations, Infrastructure
Pricing details1 tier
1Training & Certification - RISC-V Fundamentals + Foundational Associate Exam Bundle
ModelOtherBilling cadenceOther
Notes

Designed for computer engineers and programmers to gain skills in RISC-V processors, enhancing job market competitiveness. Available through the training programs section.

riscv.org
GTM typeB2B
B2B
Offering typeSoftware
Software
Core offering1 text field

RISC-V International is a non-profit standards body that develops, ratifies, and maintains the open, royalty-free RISC-V instruction set architecture (ISA) through member-led Technical Working Groups. The organization monetizes membership (Premier, Strategic, Community Organization tiers), delivers professional training and certification programs (such as the RISC-V Fundamentals + Foundational Associate exam), and operates industry events such as the RISC-V Summits to grow the global RISC-V ecosystem spanning semiconductors, data centers, AI, automotive, and aerospace.

Differentiator
Functional benefit
Problem solved
Quantifiable outcome1 of 4 values shown
  • NVIDIA shipped over 1 billion RISC-V cores in 2024
+3 more records
Product overview1 text field

RISC-V International is a non-profit standards body that develops and maintains the RISC-V instruction set architecture (ISA), an open, royalty-free standard for processor design. The organization's core product is the RISC-V ISA specifications, which are developed and ratified through contributing members within Technical Working Groups. Supporting offerings include training and certification programs (RISC-V Fundamentals + RVFA Exam Bundle), developer resources (boards, labs, technical committees), compliance frameworks, and industry events such as the RISC-V Summit Europe. The ecosystem includes diverse implementations from member companies including high-performance chips for servers, edge AI applications, and specialized processors for space and automotive industries.

Product and service5 records
1RISC-V Fundamentals + Foundational Associate (RVFA) Exam Bundle
CategoryTraining and certification
Description

A bundled training program and certification exam for computer engineers and programmers to gain validated skills in RISC-V processors, designed to enhance career competitiveness in the open-source hardware market.

2RISC-V Ratified Specifications Library
CategoryStandards and specifications
Description

A centralized repository of all ratified RISC-V instruction set architecture specifications, providing developers and implementers with a single authoritative source for the open ISA standards.

3RISC-V ISA Specifications (RVA23 Profile)
CategoryStandards and specifications
Description

The RVA23 profile is a ratified RISC-V specification providing a standardized baseline for application processor implementations, enabling consistent software ecosystem development and compliance testing across different RISC-V implementations.

4RISC-V Server Platform Specification 1.0
CategoryStandards and specifications
Description

A ratified specification enabling industry-standard boot systems for server and data center platforms built on RISC-V architecture, supporting POSIX-compliant operating systems and providing the foundation for enterprise server adoption.

5RISC-V Summit Europe 2026
CategoryIndustry events
Description

A multi-day industry conference bringing together RISC-V members, manufacturers, researchers, academics, and students for keynotes, technical sessions, tutorials, and networking to advance the RISC-V open instruction set architecture ecosystem.

Scale indicator9 records

Each record includes

Type, Value, Description, Source

Partnership15 partners
1NASA
Strategic tierCoreTypeStrategic or Co-development PartnerAnnounced on2025-01-01
Description

NASA joined the RISC-V Space Special Interest Group to develop standards for radiation-resistant spaceflight processors, along with ESA, Microchip, SiFive, and Frontgrade Gaisler.

eetimes.com
Strategic tierCoreTypeStrategic or Co-development PartnerAnnounced on2025-01-01
Description

ESA participates in the RISC-V Space SIG to develop space-grade processor standards for radiation-resistant applications.

Strategic tierCoreTypeStrategic or Co-development PartnerAnnounced on2025-01-01
Description

SiFive is a founding member of RISC-V International and participates in the Space SIG. The company is launching high-performance RISC-V chips for servers and edge applications, and received $400M Series G financing with NVIDIA as an investor.

Strategic tierCoreTypeStrategic or Co-development PartnerAnnounced on2025-01-01
Description

Microchip participates in the RISC-V Space SIG for radiation-resistant spaceflight processor standards development.

Strategic tierCoreTypeStrategic or Co-development PartnerAnnounced on2025-01-01
Description

Frontgrade Gaisler collaborates in the RISC-V Space SIG to develop standards for radiation-resistant spaceflight processors.

Strategic tierCoreTypeTechnology or IntegrationAnnounced on2024-01-01
Description

Canonical added full RVA23 support to Ubuntu 26.04 LTS, providing comprehensive operating system support for RISC-V application processors with POSIX-compliant OS environments.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

RED Semiconductor launched Ordo1 AI accelerator based on VISC architecture and is a member of RISC-V International. Partnered with Aion Silicon for test silicon and hardened IP solutions.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

Aion Silicon partnered with RED Semiconductor to deliver test silicon and hardened IP solutions for RED's Ordo1 AI accelerator.

Strategic tierCoreTypeTechnology or Integration
Description

Red Hat natively supports RISC-V architecture with major software ecosystem contributions, including PyTorch upstreaming already underway.

Strategic tierCoreTypeStrategic or Co-development Partner
Description

RISC-V International operates under the Linux Foundation umbrella, with joint events including Open Source Summit Europe and Open Source Summit India.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

Co-organizer of RISC-V Summit Europe 2026 in Bologna, Italy, representing academic partnership in advancing RISC-V ecosystem.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

Akeana is launching high-performance RISC-V chips for servers and edge applications as part of the RISC-V ecosystem.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

NextSilicon is productizing its Arbel RISC-V core into 64-core and 128-core enterprise processors for AI and HPC workloads.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

Epic Semi is launching high-performance RISC-V chips for servers and edge applications.

Strategic tierMinorTypeStrategic or Co-development Partner
Description

SpacemiT is launching high-performance RISC-V chips targeting space and edge applications.

Recent move8 records

Each record includes

Date, Type, Title, Description, Source

Expansion highlight6 records

Each record includes

Type, Description

Peers10 records
TypeBroad incumbent
Description

Intel's x86 architecture is the third major ISA alongside ARM and RISC-V, dominating data center and PC markets. Intel and RISC-V International are comparable as ISA stewards, though Intel is an integrated commercial chipmaker while RISC-V International is a non-profit standards body. The RISC-V relocation to Switzerland was explicitly motivated by escaping Intel and ARM licensing restrictions.

TypeBroad incumbent
Description

ARM is the dominant proprietary instruction set architecture and the primary alternative to RISC-V in mobile, embedded, and increasingly server markets. Both ARM and RISC-V International define processor instruction set standards, making them direct comparables in the ISA ecosystem, though ARM operates commercially with licensing fees while RISC-V International is a non-profit standards body.

TypeOthers
Description

Eclipse Foundation is a major non-profit open-source foundation managing standards and projects across software and increasingly hardware. Like RISC-V International, Eclipse is a membership-based standards organization, and both operate within the broader open-source foundation ecosystem, though Eclipse's focus is broader software tooling rather than processor ISAs.

TypeDirect peer
Description

SiFive is the leading commercial implementer of RISC-V cores, founded by RISC-V creators and serving as a primary vehicle for RISC-V commercialization. While RISC-V International is the standards body and SiFive is a chip IP vendor, both are foundational to the RISC-V ecosystem, and SiFive's $400M Series G and $3.65B valuation signal the commercial value being built on top of the RISC-V standard.

TypeBroad incumbent
Description

MIPS is a competing processor ISA historically used in embedded systems and networking, now owned by GlobalFoundries-affiliated entities. MIPS and RISC-V are comparable as alternative ISAs challenging x86 and ARM, with MIPS being the longer-established but more narrowly adopted competitor that RISC-V is now displacing in many segments.

TypeEmerging player
Description

Ventana develops high-performance RISC-V application processors for data center and cloud markets. As a member of RISC-V International and a key commercial implementer targeting server workloads, Ventana represents a critical commercial use case for the RISC-V standard and a comparable peer in the RISC-V ecosystem.

TypeEmerging player
Description

Tenstorrent is a RISC-V-based AI chip company developing high-performance processors for AI workloads. While RISC-V International is the standards body, Tenstorrent represents one of the most important commercial implementations riding on top of the RISC-V standard, with overlapping AI-native positioning and member relationship.

TypeDirect peer
Description

CHIPS Alliance is a Linux Foundation project focused on open-source hardware and chip design, sharing RISC-V International's mission of open hardware collaboration. Both are non-profit consortia fostering open hardware ecosystems, and both operate under the Linux Foundation umbrella, making CHIPS Alliance the closest organizational peer in structure and purpose.

TypeOthers
Description

Linux Foundation is the parent organization under which RISC-V International operates, jointly hosting events like Open Source Summit. As the largest open-source foundation globally, Linux Foundation is comparable as an organizational model for sustaining open-source standards bodies, though its scope is far broader than RISC-V International's ISA focus.

TypeDirect peer
Description

OpenPOWER Foundation stewards the open-source Power ISA, paralleling RISC-V International's role for the RISC-V ISA. Both are non-profit standards bodies developing open instruction set architectures, and both target server and high-performance computing markets, making OpenPOWER the most structurally analogous peer organization to RISC-V International.

Market position
Strengths5 records

Each record includes

Headline, Details, Source

Weaknesses5 records

Each record includes

Headline, Details, Source

Competitive moat5 records

Each record includes

Type, Details

Key risks6 records

Each record includes

Headline, Details, Source

Key highlights7 records

Each record includes

Headline, Details, Source

Customer concentration

Classification, Details

Named customers1 record

Each record includes

Name, Industry, Type, Use case, Source, UUID

Segment4 records

Each record includes

Title, Type, Primary, Description, Pain point addressed, Use case, Source

Ideal customer profile4 records

Each record includes

Profile, Firmographic size, Sales motion, Sales cycle length, Buying structure, Purchase trigger, Buyer persona, Geography, Industry vertical, Primary use case, Description, Pain points, Evidence proof points, Target buyer

Technology focused
Yes
API detail
Has APIbool
No

Docs URL, Description

AI capability3 records

Each record includes

Type, Description, Source

AI maturity
App detail

Has app

Feature4 records

Each record includes

Title, Differentiator, Description, Source

Core technology
Revenue estimate
Valuation estimate
Number of profiles
Profiles6 records

Each record includes

Name, Designation, Designation category, Overview, Profile commentary, Source

No data
Compliance1 record

Each record includes

Name, Class, Description

Funding overview

Funding stage, Last funding date, Total funding USD

Funding rounds

Each record includes

Round, Amount USD, Date, Pre money valuation, Total investors, Investors, News

Investors

Each record includes

Name, Type, Date of entry, Rounds participated, Website

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Each record includes

Name, Acquisition type, Announced date, Completed date, Status, Website, News

Investment

Each record includes

Name, Round, Announced date, Lead investor, Website, News

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

RISC-V International

Open Instruction Set Architecture Standardsriscv.org

RISC-V International is a non-profit standards body that develops and ratifies the open, royalty-free RISC-V instruction set architecture, serving over 4,500 member organizations across semiconductor, data center, AI, automotive, and aerospace markets.

What RISC-V International does

RISC-V International Association is a non-profit standards organization founded in 2015 and headquartered in Zurich, Switzerland, following a 2020 relocation from the United States to escape licensing restrictions imposed by Intel and ARM. The organization maintains and ratifies the RISC-V instruction set architecture (ISA), an open, royalty-free standard providing a common platform for processor design across data center, edge AI, automotive, aerospace, IoT/embedded, and HPC workloads. Recent ratified milestones include the RVA23 profile and the RISC-V Server Platform Specification 1.0 (both 2024), which establish standardized baselines for application processors and server-class boot systems respectively.

The organization generates revenue primarily through membership fees (Premier, Strategic, and Community Organization tiers) across a membership base exceeding 4,500 organizations worldwide, supplemented by training and certification programs including the RISC-V Fundamentals + Foundational Associate (RVFA) exam bundle. Its go-to-market is community-led: technical working groups ratify specifications, regional events (RISC-V Summits, World RISC-V Days) drive adoption, and software ecosystem commitments from Canonical (Ubuntu 26.04 LTS RVA23 support), Red Hat, and PyTorch upstreaming anchor developer mindshare. Notable strategic members include Nvidia, Microsoft, Google, Huawei, Tencent, and Alibaba, and the organization operates under the Linux Foundation umbrella with a small staff of 11-50 employees. The core product is the ratified RISC-V specification library; monetization derives from the standardization, certification, and governance work required to maintain an open standard used in over 1 billion cores shipped annually (NVIDIA alone, 2024).

RISC-V International firmographics

Firmographics
Name
RISC-V International
Legal name
RISC-V International Association
Website
https://riscv.org
Company type
Private
Founded year
2015
Operating status
Operating
Headcount range
11–50 employees
Short description
RISC-V International is a non-profit standards body that develops and ratifies the open, royalty-free RISC-V instruction set architecture, serving over 4,500 member organizations across semiconductor, data center, AI, automotive, and aerospace markets.
Ownership category
akta.pro rank

Where RISC-V International is headquartered

Location

Headquarters

HQ city
San Francisco
HQ country
United States
HQ region
North America

Offices1 record

Markets served

RISC-V International business model

Business model
GTM type
B2B
Offering type
Software
Cost components
Personnel, Technology or R&D, Marketing or Sales, Operations, Infrastructure

Revenue model

  1. Membership Fees: RISC-V International generates revenue through membership fees from companies and individuals. Membership options include Premier, Strategic, and Community Organization tiers. Companies join to actively influence the development of the open, royalty-free instruction set architecture.
  2. Training and Certification: RISC-V International offers training programs and certification exams, including the RISC-V Fundamentals + Foundational Associate (RVFA) exam bundle designed for computer engineers and programmers.

Pricing tiers

ModelBillingPrice
OtherOtherTraining & Certification - RISC-V Fundamentals + Foundational Associate Exam Bundle

Go-to-market motion1 record

Distribution channels1 record

Marketing channels7 records

RISC-V International product offering

Product offering

Core offering

RISC-V International is a non-profit standards body that develops, ratifies, and maintains the open, royalty-free RISC-V instruction set architecture (ISA) through member-led Technical Working Groups. The organization monetizes membership (Premier, Strategic, Community Organization tiers), delivers professional training and certification programs (such as the RISC-V Fundamentals + Foundational Associate exam), and operates industry events such as the RISC-V Summits to grow the global RISC-V ecosystem spanning semiconductors, data centers, AI, automotive, and aerospace.

Product overview

RISC-V International is a non-profit standards body that develops and maintains the RISC-V instruction set architecture (ISA), an open, royalty-free standard for processor design. The organization's core product is the RISC-V ISA specifications, which are developed and ratified through contributing members within Technical Working Groups. Supporting offerings include training and certification programs (RISC-V Fundamentals + RVFA Exam Bundle), developer resources (boards, labs, technical committees), compliance frameworks, and industry events such as the RISC-V Summit Europe. The ecosystem includes diverse implementations from member companies including high-performance chips for servers, edge AI applications, and specialized processors for space and automotive industries.

Differentiator

Problem solved

Functional benefit

Products and services

  • RISC-V Fundamentals + Foundational Associate (RVFA) Exam Bundle A bundled training program and certification exam for computer engineers and programmers to gain validated skills in RISC-V processors, designed to enhance career competitiveness in the open-source hardware market.
  • RISC-V Ratified Specifications Library A centralized repository of all ratified RISC-V instruction set architecture specifications, providing developers and implementers with a single authoritative source for the open ISA standards.
  • RISC-V ISA Specifications (RVA23 Profile) The RVA23 profile is a ratified RISC-V specification providing a standardized baseline for application processor implementations, enabling consistent software ecosystem development and compliance testing across different RISC-V implementations.
  • RISC-V Server Platform Specification 1.0 A ratified specification enabling industry-standard boot systems for server and data center platforms built on RISC-V architecture, supporting POSIX-compliant operating systems and providing the foundation for enterprise server adoption.
  • RISC-V Summit Europe 2026 A multi-day industry conference bringing together RISC-V members, manufacturers, researchers, academics, and students for keynotes, technical sessions, tutorials, and networking to advance the RISC-V open instruction set architecture ecosystem.

Quantifiable outcome

  • NVIDIA shipped over 1 billion RISC-V cores in 2024
  • +3 more outcomes

Companies that use RISC-V International

Customer profile

Named customers1 record

Segments4 records

Ideal customer profiles4 records

RISC-V International technology and API

Technology

Technology focussed Yes

API detail

Has API
No
API docs
API detail

Core technology

AI maturity

App detail

AI capability3 records

Feature4 records

RISC-V International partnerships and signals

Strategic signal

Partnerships

15 partnerships are on record, tiered core and minor.

  • NASAcoreStrategic or Co-development Partner · 1 January 2025NASA joined the RISC-V Space Special Interest Group to develop standards for radiation-resistant spaceflight processors, along with ESA, Microchip, SiFive, and Frontgrade Gaisler.
  • European Space Agency (ESA)coreStrategic or Co-development Partner · 1 January 2025ESA participates in the RISC-V Space SIG to develop space-grade processor standards for radiation-resistant applications.
  • SiFivecoreStrategic or Co-development Partner · 1 January 2025SiFive is a founding member of RISC-V International and participates in the Space SIG. The company is launching high-performance RISC-V chips for servers and edge applications, and received $400M Series G financing with NVIDIA as an investor.
  • MicrochipcoreStrategic or Co-development Partner · 1 January 2025Microchip participates in the RISC-V Space SIG for radiation-resistant spaceflight processor standards development.
  • Frontgrade GaislercoreStrategic or Co-development Partner · 1 January 2025Frontgrade Gaisler collaborates in the RISC-V Space SIG to develop standards for radiation-resistant spaceflight processors.
  • CanonicalcoreTechnology or Integration · 1 January 2024Canonical added full RVA23 support to Ubuntu 26.04 LTS, providing comprehensive operating system support for RISC-V application processors with POSIX-compliant OS environments.
  • RED SemiconductorminorStrategic or Co-development PartnerRED Semiconductor launched Ordo1 AI accelerator based on VISC architecture and is a member of RISC-V International. Partnered with Aion Silicon for test silicon and hardened IP solutions.
  • Aion SiliconminorStrategic or Co-development PartnerAion Silicon partnered with RED Semiconductor to deliver test silicon and hardened IP solutions for RED's Ordo1 AI accelerator.
  • Red HatcoreTechnology or IntegrationRed Hat natively supports RISC-V architecture with major software ecosystem contributions, including PyTorch upstreaming already underway.
  • Linux FoundationcoreStrategic or Co-development PartnerRISC-V International operates under the Linux Foundation umbrella, with joint events including Open Source Summit Europe and Open Source Summit India.
  • University of BolognaminorStrategic or Co-development PartnerCo-organizer of RISC-V Summit Europe 2026 in Bologna, Italy, representing academic partnership in advancing RISC-V ecosystem.
  • AkeanaminorStrategic or Co-development PartnerAkeana is launching high-performance RISC-V chips for servers and edge applications as part of the RISC-V ecosystem.
  • NextSiliconminorStrategic or Co-development PartnerNextSilicon is productizing its Arbel RISC-V core into 64-core and 128-core enterprise processors for AI and HPC workloads.
  • Epic SemiminorStrategic or Co-development PartnerEpic Semi is launching high-performance RISC-V chips for servers and edge applications.
  • SpacemiTminorStrategic or Co-development PartnerSpacemiT is launching high-performance RISC-V chips targeting space and edge applications.

Scale indicators9 records

Recent moves8 records

Expansion highlights6 records

RISC-V International competitors and assessment

Company assessment

Broad incumbents

  • Intel Corporation: Intel's x86 architecture is the third major ISA alongside ARM and RISC-V, dominating data center and PC markets. Intel and RISC-V International are comparable as ISA stewards, though Intel is an integrated commercial chipmaker while RISC-V International is a non-profit standards body. The RISC-V relocation to Switzerland was explicitly motivated by escaping Intel and ARM licensing restrictions.
  • ARM Holdings: ARM is the dominant proprietary instruction set architecture and the primary alternative to RISC-V in mobile, embedded, and increasingly server markets. Both ARM and RISC-V International define processor instruction set standards, making them direct comparables in the ISA ecosystem, though ARM operates commercially with licensing fees while RISC-V International is a non-profit standards body.
  • MIPS Technology: MIPS is a competing processor ISA historically used in embedded systems and networking, now owned by GlobalFoundries-affiliated entities. MIPS and RISC-V are comparable as alternative ISAs challenging x86 and ARM, with MIPS being the longer-established but more narrowly adopted competitor that RISC-V is now displacing in many segments.

Others

  • Eclipse Foundation: Eclipse Foundation is a major non-profit open-source foundation managing standards and projects across software and increasingly hardware. Like RISC-V International, Eclipse is a membership-based standards organization, and both operate within the broader open-source foundation ecosystem, though Eclipse's focus is broader software tooling rather than processor ISAs.
  • Linux Foundation: Linux Foundation is the parent organization under which RISC-V International operates, jointly hosting events like Open Source Summit. As the largest open-source foundation globally, Linux Foundation is comparable as an organizational model for sustaining open-source standards bodies, though its scope is far broader than RISC-V International's ISA focus.

Direct peers

  • SiFive: SiFive is the leading commercial implementer of RISC-V cores, founded by RISC-V creators and serving as a primary vehicle for RISC-V commercialization. While RISC-V International is the standards body and SiFive is a chip IP vendor, both are foundational to the RISC-V ecosystem, and SiFive's $400M Series G and $3.65B valuation signal the commercial value being built on top of the RISC-V standard.
  • CHIPS Alliance: CHIPS Alliance is a Linux Foundation project focused on open-source hardware and chip design, sharing RISC-V International's mission of open hardware collaboration. Both are non-profit consortia fostering open hardware ecosystems, and both operate under the Linux Foundation umbrella, making CHIPS Alliance the closest organizational peer in structure and purpose.
  • OpenPOWER Foundation: OpenPOWER Foundation stewards the open-source Power ISA, paralleling RISC-V International's role for the RISC-V ISA. Both are non-profit standards bodies developing open instruction set architectures, and both target server and high-performance computing markets, making OpenPOWER the most structurally analogous peer organization to RISC-V International.

Emerging players

  • Ventana Micro Systems: Ventana develops high-performance RISC-V application processors for data center and cloud markets. As a member of RISC-V International and a key commercial implementer targeting server workloads, Ventana represents a critical commercial use case for the RISC-V standard and a comparable peer in the RISC-V ecosystem.
  • Tenstorrent: Tenstorrent is a RISC-V-based AI chip company developing high-performance processors for AI workloads. While RISC-V International is the standards body, Tenstorrent represents one of the most important commercial implementations riding on top of the RISC-V standard, with overlapping AI-native positioning and member relationship.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

RISC-V International social profiles

Digital presence

RISC-V International compliance and trust

Trust signal

Compliance1 record

RISC-V International financial estimates

Financial estimate

Revenue estimate

Valuation estimate

RISC-V International leadership team

Management profile

Number of profiles

Profiles6 records

RISC-V International funding detail

Funding detail

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

RISC-V International M&A and investment

M&A and investment

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about RISC-V International

What does RISC-V International do?

RISC-V International is a non-profit standards body that develops, ratifies, and maintains the open, royalty-free RISC-V instruction set architecture (ISA) through member-led Technical Working Groups. The organization monetizes membership (Premier, Strategic, Community Organization tiers), delivers professional training and certification programs (such as the RISC-V Fundamentals + Foundational Associate exam), and operates industry events such as the RISC-V Summits to grow the global RISC-V ecosystem spanning semiconductors, data centers, AI, automotive, and aerospace.

Is RISC-V International a public or private company?

RISC-V International is a private company. It is classified as nonprofit foundation owned and is currently operating.

When was RISC-V International founded?

RISC-V International was founded in 2015. It employs 11 to 50 people.

Where is RISC-V International based?

RISC-V International is headquartered in San Francisco, United States, in the North America region.

How does RISC-V International make money?

Two revenue lines are on record. Membership Fees are the primary driver. The others are training and Certification.

Who are RISC-V International's main competitors?

Broad incumbents on record are Intel Corporation, ARM Holdings and MIPS Technology. Others are Eclipse Foundation and Linux Foundation. Direct peers are SiFive, CHIPS Alliance and OpenPOWER Foundation. Emerging players are Ventana Micro Systems and Tenstorrent.

Does RISC-V International have an API?

No public API is recorded for RISC-V International.

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Live signals
South China Morning PostHow US-China tech ties are deepening as RISC-V chips go mainstreamMIPS, acquired by GlobalFoundries, is collaborating with Chinese firms on RISC-V standardization, according to a senior executive in Shanghai. The effort is part of RISC-V International's broader initiatives to unite global players, including US, European, and Chinese entities, to standardize technologies from AI to data centre servers.SubstackWhere will RISC-V be in 20 Years? Poll ResultsA poll of Chip Letter readers asked about RISC-V's future; in August 2023, a majority expected it to be the standard ISA by 2043, but by August 2026, less than half of voters held that view, a 22% drop. The author attributes the shift to AI investment diverting attention and competing architectures like Intel and Arm gaining ground.HpcwireSince 1987 – Covering the Fastest Computers in the World and the People Who Run ThemMIPS, by GF, announced on August 27, 2026 that it has become a Premier Member of RISC-V International, with Yankin Tanurhan, SVP & CTO of MIPS, appointed Vice Chairman of the RISC-V International Board. MIPS serves on several RISC-V committees, task groups and SIGs covering automotive, functional safety, crypto, vector and documentation. GF said the move reinforces its strategic investment in RISC-V.Business Wire BlogMIPS Leads Open Standards Development for Physical AI Platforms as RISC-V International Premier MemberMIPS, by GF, announced it has become a Premier Member of RISC-V International, with Yankin Tanurhan, SVP & CTO of MIPS, appointed Vice Chairman of the RISC-V International Board. The company serves on several RISC-V committees, task groups and SIGs covering automotive, functional safety, crypto, vector and documentation.IndexBoxHardware/Software Co-Design: Evolution, Challenges, and Future Trends in 2026The article analyzes the 30-year evolution of hardware/software co-design, highlighting that while early technologies were abandoned, current industry trends driven by AI and power efficiency are reviving the need for integrated design flows. It notes that hyperscalers and IP companies like RISC-V are increasingly optimizing silicon for specific workloads to address thermal and performance constraints in edge and data center environments. The report concludes that despite progress in individual processor design, fundamental divides remain between software and hardware teams, with EDA tooling improvements needed to manage system-level complexity.BusinessLineIIT Madras to host Digital India RISC-V Symposium 2026 on semiconductor innovationIIT Madras, in partnership with MeitY and RISC-V International, will host the Digital India RISC-V Symposium 2026 on August 1-2, 2026, at its Research Park in Chennai. The third edition of the symposium, themed 'Empowering Bharat's Semiconductor Future,' aims to bring together policymakers, researchers, startups, industry leaders, and investors to collaborate on secure and trusted semiconductor technologies for India's digital economy. Participants can explore live technology demonstrations, startup exhibits, and networking opportunities in processor design, AI hardware, and cybersecurity.RediffDigital India RISC-V Symposium To Boost Semiconductor InnovationIIT Madras is hosting the 3rd Digital India RISC-V Symposium 2026 from August 1-2 in Chennai, in partnership with MeitY and RISC-V International, to advance indigenous processor technologies and establish India as a global semiconductor hub. The symposium will bring together policymakers, technology experts, researchers, startups, industry leaders, and students to collaborate on secure computing, AI, and the RISC-V ecosystem. Professor V Kamakoti stated that the event reflects India's intellectual capital and innovation ecosystem for achieving semiconductor leadership.EetimesRISC-V Is Inevitable, State of the Union Keynote ArguesAt the RISC-V Summit Europe 2026 in Bologna, Italy, Krste Asanović (chief architect at SiFive and RISC-V International) declared the state of the RISC-V union "strong," positioning the open-standard ISA for a major push into enterprise data centers and server farms. The arrival of RVA23-compliant server-class silicon marks a historic inflection point, enabling major technology companies including Qualcomm, Nvidia, Meta, Google, and Alibaba to incorporate RISC-V into their products. Asanović also introduced optimization guidance options (Oilsm, Ovlt) to align hardware and software performance expectations, advanced the CHERI security architecture as a new base ISA (RV32Y/RV64Y), and outlined expanded DSP capabilities for AI accelerator applications.EetimesRISC-V Targets Data Centers, Edge AI, SpaceAt the RISC-V Summit Europe 2026 in Bologna, RISC-V International announced that the open-standard instruction set architecture has matured and is now targeting data centers, edge AI, and space exploration markets, with the RISC-V Server Platform Specification 1.0 ratified in 2024 enabling industry-standard boot systems. Companies such as SiFive, Akeana, NextSilicon, Epic Semi, and SpacemiT are launching high-performance RISC-V chips for servers and edge applications, while Microsoft has joined as a top board member and Canonical has added full RVA23 support to Ubuntu 26.04 LTS. In space applications, a RISC-V Space Special Interest Group formed at the end of 2025 brings together NASA, ESA, Microchip, SiFive, and Frontgrade Gaisler to develop standards for radiation-resistant spaceflight processors.EetimesRISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open HardwareRISC-V Summit Europe 2026 will take place June 8–12, 2026, at the Palazzo dei Congressi in Bologna, Italy, bringing together industry members, manufacturers, researchers, academics, and students to advance the RISC-V open instruction set architecture ecosystem. The summit is organized by RISC-V International, the University of Bologna, and Planning, with a program covering sessions on embedded systems, AI, automotive, high-performance computing, security, space, and open hardware research. Notable sessions include presentations from Luxottica on smart glasses, VRULL GmbH on matrix extensions, and Qualcomm on security isolation techniques, alongside EU-backed initiatives like TRISTAN aimed at industrializing the European RISC-V ecosystem.