Name

CHIPS Alliance

Legal name

CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance

Website

https://chipsalliance.org

Company type

Private

Founded year

2019

Operating status

Operating

Headcount range

11–50 employees

Ownership category

akta.pro rank

Product category

Open Source Hardware IP

NAICS

Computer Systems Design and Related Services (5415), Semiconductor and Related Device Manufacturing (334413)

SIC

Semiconductors & Related Devices (3674), Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF)

akta.pro secondary industries

Hardware Security EDA & IP (Secure Design, PUF, Crypto, Anti-Tamper) (HDAHAFAK), IP Enablement, Characterization & Porting Services (HDAHAFAI), Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH), Security & Trusted Hardware ICs (Secure Element/TPM/Crypto) (HDAHABAF)

Keywords

• Open source hardware
• RISC-V cores
• Silicon IP development
• EDA tooling
• Root of Trust

Headquarters

HQ city

San Francisco

HQ country

United States

HQ region

North America

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales, Others

Revenue model

1. Membership Dues: CHIPS Alliance is a Linux Foundation project funded through organizational membership dues. The Board approved a 25% adjustment in membership dues for 2026 to build financial reserves and ensure sustainable operations. This is a collaborative, non-profit consortium model.
2. Open Source Project Hosting: As an open source alliance, CHIPS Alliance provides collaborative development infrastructure for member organizations to jointly develop and share hardware IP, tools, and specifications without direct revenue generation from licensing.

Go-to-market motion1 record

Distribution channels2 records

Marketing channels7 records

Core offering

CHIPS Alliance develops and hosts open source hardware designs for silicon devices and FPGAs, including RISC-V CPU cores (VeeR family), Root of Trust IP (Caliptra), reference SoC designs (Guineveer), and a suite of open source EDA tools (Verible, Verilator, Topwrap, RISC-V DV). All projects are released under Apache 2.0 license and developed collaboratively by 53 member organizations including AMD, Google, Microsoft, NVIDIA, Intel, and Qualcomm.

Product overview

CHIPS Alliance is a Linux Foundation project that develops and hosts high-quality open source hardware designs, including RISC-V CPU cores (VeeR family: EH1, EH2, EL2), reference SoC designs (Guineveer), security IP (Caliptra Root of Trust), and I/O peripherals (I3C core). The alliance also provides open source tooling for chip design and verification, including Verible (SystemVerilog parser), RISC-V DV (verification framework), Topwrap (HDL design aggregation), and the FPGA Interchange Format. Projects are governed under Apache 2.0 license and supported by 53 member organizations including AMD, Google, Microsoft, Qualcomm, NVIDIA, Intel, and multiple universities.

Differentiator

Problem solved

Functional benefit

Products and services

• VeeR RISC-V Core Family Family of production-grade RISC-V CPU cores hosted by CHIPS Alliance, including EH1 (high-performance single-threaded RV32IMCZ), EH2 (dual-threaded successor), and EL2 (tiny, low-power RV32IMC). Released as open source RTL under Apache 2.0 license for use in custom SoC designs.
• Caliptra Root of Trust Open source silicon Root of Trust (RoT) specification and implementation providing device identity, measured boot, and attestation for datacenter-class SoCs including CPUs, GPUs, DPUs, and TPUs. Co-founded by AMD, Google, Microsoft, and NVIDIA.
• Guineveer RISC-V Reference SoC Simple and extensible reference SoC design based on VeeR EL2 core that serves as baseline for custom SoC development, integrating OpenTitan UART, I3C core, and AXI building blocks. Created by Antmicro.
• I3C Core Open source implementation of the I3C target functionality of the I3C bus protocol (MIPI Alliance), supporting OCP recovery flow for DDR5 and PCIe device management. Used in Caliptra and Guineveer.
• Verible Open source SystemVerilog parser developed by Google providing linting, formatting, indexing, and Language Server Protocol (LSP) integration for collaborative hardware development environments.
• RISC-V DV Open source instruction generator for RISC-V processors for verification, generating random instruction chains executed simultaneously through RTL simulation and ISS reference models.
• Topwrap Open source toolkit for modular, parameterizable digital logic design that automates HDL module connection, interface grouping, and top-level design generation through YAML-based descriptions.
• Verilator Open source SystemVerilog simulator used for simulation and testing, with ongoing CHIPS Alliance contributions toward enabling UVM support and SystemVerilog features.
• FPGA Interchange Format Standard format for FPGA architecture description enabling interoperability between open source tools (Yosys, VPR, nextpnr) and proprietary tooling (Vivado, RapidWright).
• Rowhammer Testing Framework Open source FPGA-based testing platform for detecting and experimenting with Rowhammer vulnerability in DDR and LPDDR memory chips, developed with Google.
• OpenPRoT Portable open-source firmware stack for silicon Roots of Trust (RoT) platforms, currently in architecture phase with contributions from AMD and Google.

Quantifiable outcome

• Lower development costs through shared infrastructure and collaborative IP development
• +3 more outcomes

Named customers19 records

Segments4 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature10 records

Partnerships

13 partnerships are on record, tiered core, flagship, minor and exploratory.

• Open Compute Project FoundationcoreStrategic or Co-development Partner · 13 December 2022Caliptra hardware specification is hosted by Open Compute Project Foundation while CHIPS Alliance oversees the open source RTL implementation. This collaboration tightens the bond between CHIPS Alliance and OCP for Composable Security Architecture development.
• Linux FoundationcoreStrategic or Co-development PartnerCHIPS Alliance is a Linux Foundation project hosted under its umbrella. The Linux Foundation provides governance framework, project management support, marketing infrastructure, and operational infrastructure for the consortium.
• AMDflagshipStrategic or Co-development PartnerAMD co-founded Caliptra with Google, Microsoft, and NVIDIA. Platinum member of CHIPS Alliance contributing to VeeR RISC-V cores, security architecture (Composable Security Architecture), and open source hardware ecosystem development.
• GoogleflagshipStrategic or Co-development PartnerGoogle co-founded Caliptra and is a Platinum member of CHIPS Alliance. Major contributor to Verible, RISC-V VeeR cores, open source EDA tooling, and Google Cloud-based verification and CI/CD infrastructure.
• MicrosoftflagshipStrategic or Co-development PartnerMicrosoft joined as Platinum member contributing to Caliptra Root of Trust project. Developing sovereign cloud architecture using open source hardware security technologies including Caliptra and OCP SAFE.
• NVIDIAflagshipStrategic or Co-development PartnerNVIDIA co-founded Caliptra and joined CHIPS Alliance as Silver member. Contributing to Root of Trust development for datacenter-class SoCs including GPUs.
• AntmicroflagshipTechnology or IntegrationPlatinum member and key technical contributor developing Topwrap, Guineveer, Verilator enhancements, RISC-V tooling, DDR Rowhammer testing frameworks, and numerous open source hardware projects within CHIPS Alliance.
• Western DigitalcoreTechnology or IntegrationSilver member contributing to open source verification tools development including UVM support in Verilator, RISC-V based storage solutions, and collaborative EDA tooling ecosystem.
• RISC-V InternationalcoreStrategic or Co-development PartnerRISC-V is an Associate member of CHIPS Alliance. The VeeR RISC-V core family and various CHIPS projects are compatible with and contribute to the RISC-V ecosystem.
• OpenPOWER FoundationminorStrategic or Co-development PartnerOpenPOWER Foundation is an Associate member. Collaborative efforts in LibreBMC project for open source board management controllers compatible with OCP's DC-SCM standard.
• lowRISCcoreTechnology or IntegrationlowRISC (steward of OpenTitan) collaborates with CHIPS Alliance on security projects. OpenTitan UART is integrated into Guineveer SoC reference design.
• Coral NPU ProjectexploratoryStrategic or Co-development PartnerDiscussions underway regarding potential contribution of Google's Coral NPU to CHIPS Alliance, which would provide a full-stack, open-source platform for edge AI.
• JEDEC Standards OrganizationminorStrategic or Co-development PartnerCHIPS Alliance contributes to JEDEC Rowhammer mitigation standardization efforts through open source testing platforms and research collaboration with memory manufacturers.

Scale indicators6 records

Recent moves6 records

Expansion highlights6 records

Direct peers

• lowRISC: lowRISC is a non-profit that stewards OpenTitan, Google's open source silicon Root of Trust project. lowRISC collaborates directly with CHIPS Alliance (OpenTitan UART integrated into Guineveer SoC), and both organizations compete for security IP mindshare in open source hardware.
• OpenHW Group: OpenHW Group is a non-profit, open source hardware organization delivering CORE-V processor IP and supporting pre-silicon verification. It operates a similar Linux Foundation-adjacent model and directly competes with CHIPS Alliance for contributor mindshare in the RISC-V IP ecosystem.
• RISC-V International: RISC-V International is the non-profit standards body governing the RISC-V ISA. CHIPS Alliance's VeeR core family and other projects implement RISC-V specifications and contribute back to the ecosystem. RISC-V International is also an Associate member of CHIPS Alliance, making them directly aligned collaborators in open hardware.
• SiFive: SiFive is the leading commercial RISC-V IP vendor offering production-grade RISC-V cores, software tooling, and developer boards. SiFive is also a Platinum member of CHIPS Alliance but represents the commercial alternative that competes with CHIPS Alliance's open source VeeR cores for design wins.
• Open Compute Project Foundation: Open Compute Project Foundation hosts the Caliptra hardware specification in partnership with CHIPS Alliance, which oversees the open source RTL implementation. Both organizations pursue collaborative open source hardware development with overlapping membership from hyperscalers and semiconductor companies.
• OpenPOWER Foundation: OpenPOWER Foundation is a non-profit open hardware consortium focused on the POWER architecture. OpenPOWER is an Associate member of CHIPS Alliance, and both organizations pursue similar collaborative IP development models under the broader open hardware banner.

Broad incumbents

• Arm: Arm is the dominant commercial processor IP vendor with extensive ISA and core IP portfolios across mobile, embedded, and increasingly datacenter markets. Arm competes broadly with CHIPS Alliance RISC-V IP for design wins, though it operates a much larger commercial model with licensing fees.
• Synopsys: Synopsys is a leading EDA and commercial semiconductor IP vendor, and is a Silver member of CHIPS Alliance. Synopsys competes with CHIPS Alliance's open source EDA tooling (Verible, Verilator, Topwrap) while also contributing to verification efforts within the alliance.

Others

• Eclipse Foundation: Eclipse Foundation hosts open source projects and working groups for hardware-adjacent tooling, including projects relevant to EDA and embedded development. It represents an alternative open source foundation model with overlapping tooling and developer communities to CHIPS Alliance.
• Linux Foundation: Linux Foundation is the parent organization hosting CHIPS Alliance. It provides governance infrastructure, project management, legal frameworks, and financial administration for CHIPS Alliance and hundreds of other open source projects, making it the operational enabler for the alliance.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat4 records

Key risks5 records

Key highlights6 records

Customer concentration

• GitHubgithub.com/chipsalliance
• YouTubeyoutube.com/playlist?list=PLWm-dtUGVJtDrlp3GGgvsN_6kiJ4xYOSU
• LinkedInlinkedin.com/company/chipsalliance/?viewAsMember=true
• Xx.com/chipsalliance

Revenue estimate

Valuation estimate

Number of profiles

Profiles3 records

Funding overview

Funding rounds

Investors

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M&A

Investments

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Frequently asked questions about CHIPS Alliance