Name

CXL Consortium

Legal name

Compute Express Link Consortium, Inc.

Website

https://computeexpresslink.org

Company type

Private

Founded year

2019

Operating status

Operating

Headcount range

11–50 employees

Ownership category

akta.pro rank

Product category

Interconnect Standards

NAICS

Professional Organizations (81392), Business Associations (813910)

SIC

Services-Membership Organizations (8600)

akta.pro primary industry

AI Interconnects & Fabric (NVLink/CXL/PCIe/Switches) (HDAAAAAD)

akta.pro secondary industries

Technical Committees, Working Groups & Expert Panels (BPADANAB), Conformity Assessment, Testing, Inspection & Certification Cooperation (BPADANAD)

Keywords

• Interconnect specifications
• Cache coherent interconnect
• Memory pooling standards
• Memory expansion protocol
• Standards consortium

Headquarters

HQ city

Beaverton

HQ country

United States

HQ region

North America

Offices1 record

Markets served

GTM type

B2B

Offering type

Services

Cost components

Personnel, Operations, Technology or R&D, Marketing or Sales

Revenue model

1. Contributor Membership Dues: Contributor-level membership costs $10,000 per year. This tier allows companies to participate in technical working groups, influence the direction of the technology, and access intermediate (dot-level) specifications.
2. Adopter Membership (Free): Adopter membership is free following execution of the Adopter Agreement. Adopters can access final specifications (e.g., 1.0, 2.0) but not intermediate specifications, and implement with IP protections as outlined in the agreements. No revenue is generated from this tier.

Pricing tiers

Go-to-market motion1 record

Distribution channels3 records

Marketing channels8 records

Core offering

CXL Consortium develops and publishes the Compute Express Link (CXL) specification, an open industry-standard cache-coherent interconnect for processors, memory expansion, and accelerators. The consortium provides the specification documents (currently CXL 4.0), operates a Compliance Program with an Integrators List to validate implementations, and distributes technical resources including white papers, webinars, and a member portal (Causeway) for working group participation. The consortium does not manufacture products but licenses specifications through Contributor ($10,000/year) and free Adopter membership tiers.

Product overview

CXL Consortium is an industry standards organization that publishes the Compute Express Link (CXL) specification, a cache-coherent interconnect standard for processors, memory expansion, and accelerators. The Consortium's core offerings include the CXL 4.0, 3.1, 3.0, and 2.0 specifications (with past specifications available for evaluation), a Compliance Program for testing implementations, and a Resource Library containing technical training materials, white papers, presentations, and demos. The Consortium does not manufacture products but provides the specification standard and conformance testing framework for member companies to implement CXL-compliant devices and systems.

Differentiator

Problem solved

Functional benefit

Products and services

• CXL 4.0 Specification The latest generation of the Compute Express Link specification that doubles bandwidth from 64GTs to 128GTs, adds bundled port support for combining device ports between Host and CXL accelerators, and enhances memory RAS features for improved reliability and error visibility. Targeted at semiconductor, memory, server, and cloud ecosystem members building compliant processors, accelerators, memory modules, and data center infrastructure.
• CXL 3.1 Specification Feature update to CXL 3.0 expanding fabric connectivity and memory sharing/pooling capabilities, including advanced switching, peer-to-peer communications, and fine-grained resource sharing across multiple compute domains. Targeted at semiconductor, server, and cloud members building composable disaggregated infrastructure.
• CXL 3.0 Specification Specification enabling composable disaggregated systems with expanded fabric capabilities, fabric management, peer-to-peer communications, and doubled data rate to 64 GT/s with no added latency while maintaining backward compatibility. Targeted at semiconductor, server, memory, and cloud members building composable infrastructure.
• CXL 2.0 Specification Second-generation specification introducing support for switching, memory pooling, and persistent memory while preserving backward compatibility with CXL 1.1 and 1.0. Adds CXL IDE link-level security. Targeted at semiconductor, memory, and server members building pooled, switch-fabric memory systems.
• CXL 1.0/1.1 Specifications First-generation CXL specifications defining the foundational cache-coherent interconnect standard for processors, memory expansion, and accelerators. Made available as past specifications under click-through evaluation license. Targeted at developers and implementors evaluating legacy CXL implementations.
• CXL Compliance Program and Integrators List Compliance testing program that verifies CXL implementations meet specification requirements, paired with a public Integrators List documenting companies whose products have passed compliance testing. Targeted at member companies implementing CXL and at buyers seeking validated CXL-compliant products.

Quantifiable outcome

• CXL 4.0 doubles bandwidth from 64GTs to 128GTs with zero added latency
• +3 more outcomes

Named customers14 records

Segments5 records

Ideal customer profiles4 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature10 records

Partnerships

Five partnerships are on record, tiered core.

• DMTF (Distributed Management Task Force)coreStrategic or Co-development Partner · 1 October 2023DMTF and CXL Consortium established a work register under DMTF's Alliance Partner program, outlining areas of technical collaboration between the two organizations. DMTF creates open manageability standards spanning cloud, virtualization, network, servers, and storage. The collaboration enables interoperable management across CXL-enabled platforms using DMTF standards.
• PCI-SIGcoreStrategic or Co-development PartnerCXL Consortium and PCI-SIG signed a memorandum of understanding (MOU) to establish a liaison framework between the two organizations for consistent joint messaging and marketing. Both organizations work together to increase awareness of industry standard interconnect technologies and to provide collaborative, educational messaging for the developer community and computing industry. CXL.io is based on PCIe technology.
• SNIA (Storage Networking Industry Association)coreStrategic or Co-development PartnerSNIA and CXL Consortium formed a strategic alliance to enable education and support adoption of their technologies by developers, implementors, and end users. The collaboration focuses on joint marketing efforts between the CXL Marketing Work Group and the SNIA Compute, Memory, and Storage Initiative (CMSI) Marketing Committee.
• CXL Consortium Board Members (Alibaba, AMD, Arm, Astera Labs, Cisco, Dell, Google, HPE, Huawei, Intel, Meta, Microsoft, NVIDIA, Samsung, SK Hynix)coreStrategic or Co-development PartnerThe Board of Directors comprises 15 major technology companies that govern the consortium, set technical direction, and lead working groups. Board members contribute to specification development, compliance programs, and ecosystem development. They include semiconductor companies, cloud providers, server OEMs, and memory manufacturers.
• CXL Consortium Contributor MemberscoreStrategic or Co-development PartnerContributor members (over 50 companies) participate in technical working groups and have access to intermediate specifications. Members include semiconductor IP companies (Cadence, Synopsys, Arteris), memory companies (Micron, Rambus, Kioxia), test equipment vendors (Keysight, Teledyne LeCroy, Viavi), server/infrastructure companies (Lenovo, Oracle, Fujitsu), and AI companies (Panmnesia, Liqid).

Scale indicators3 records

Recent moves7 records

Expansion highlights5 records

Direct peers

• PCI-SIG: PCI-SIG is the industry consortium that develops the PCI Express (PCIe) standard on which CXL.io is directly based. CXL and PCI-SIG maintain a formal MOU for joint messaging and collaborate on the underlying interconnect technology, making PCI-SIG the closest structural and technical peer to CXL Consortium.
• UCIe Consortium: UCIe (Universal Chiplet Interconnect Express) is an open standard consortium defining chiplet-to-chiplet interconnects, with members including Intel, AMD, TSMC, and Samsung. It is structurally analogous to CXL — industry-funded, member-governed, spec-driven — and targets the adjacent die-level coherent interconnect space, making it a direct structural peer.
• CCIX Consortium: CCIX (Cache Coherent Interconnect for Accelerators) was a competing open standard for cache-coherent accelerator interconnects, with many of the same semiconductor members as CXL. While CCIX activity has substantially subsided in favor of CXL, it remains a historically direct peer illustrating the alternatives CXL displaced.
• Gen-Z Consortium: Gen-Z was an open memory fabric standard that directly competed with CXL in the coherent memory interconnect space; several CXL board members (notably SK hynix) previously served on the Gen-Z board. Gen-Z's assets were transferred to SNIA in 2022, but it remains a structurally and technically comparable peer organization.

Emerging players

• UALink Consortium: UALink (Ultra Accelerator Link) was formed in 2024 by AMD, Broadcom, Cisco, Google, HPE, Intel, Meta, and Microsoft to define an open accelerator-to-accelerator fabric. It directly overlaps CXL's accelerator attach use case and represents an emerging competitive threat to CXL's role as the open coherent interconnect for AI infrastructure.

Broad incumbents

• JEDEC: JEDEC is the broader, long-established standards body governing memory technologies (DDR, HBM, etc.) on which CXL-attached memory modules depend. CXL memory pooling and Type 3 devices build on JEDEC-defined memories, making JEDEC a complementary but broader incumbent peer.

Others

• SNIA (Storage Networking Industry Association): SNIA is a formal alliance partner of CXL Consortium, with a joint marketing relationship through its Compute, Memory, and Storage Initiative. It is a thematically adjacent industry association that influences the storage and memory standards landscape CXL intersects with.
• DMTF (Distributed Management Task Force): DMTF develops open manageability standards (e.g., Redfish) and is a formal alliance partner of CXL with an active work register for technical collaboration on CXL-enabled platform management. It is an enabling peer whose standards complement CXL deployments.
• Open Compute Project: OCP is a community-driven consortium developing open hardware designs for hyperscale data centers, overlapping with CXL's data center infrastructure and memory pooling themes. Many CXL board members (Meta, Microsoft, Google, Intel) actively contribute to OCP, making it a thematically adjacent ecosystem peer.
• InfiniBand Trade Association: The InfiniBand Trade Association governs the InfiniBand high-performance networking standard, which competes with CXL and Ethernet-based fabrics for cluster interconnects in HPC and AI infrastructure. It is an adjacent, enabling standards body serving a partially overlapping customer base.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks7 records

Key highlights7 records

Customer concentration

• YouTubeyoutube.com/channel/UCg6onUPJCLKEH0guqDuAeFA/featured
• LinkedInlinkedin.com/company/cxl-consortium
• Xx.com/ComputeExLink

Compliance2 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles15 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about CXL Consortium