Perfectus Technology Inc

What Perfectus Technology Inc does

Perfectus Technology Inc (also branded Perfectus Corporation) is a private semiconductor intellectual-property vendor headquartered in Santa Clara, California, with engineering centers in Bangalore and Bhubaneswar, India. The company builds SystemVerilog-based Verification IP (VIP) and matched Design IP for chip and System-on-Chip (SoC) designers, with a portfolio that spans the core connectivity, storage, and memory protocols — USB 2.0/3.0, PCI Express, SATA, SAS, Fibre Channel, Ethernet, AMBA, SPI 4.2, SMBUS, ONFi, and OCP on the VIP side, and controllers/expositors such as FBDIMM Controller, SAS Expander, SATA Controller, AMB Core, OCP Controller, and SMBUS Master Controller on the design side. Technology is delivered as reusable, standards-aligned testbenches and synthesizable RTL blocks that plug into customer verification and implementation flows.

The revenue model combines two streams. The first is licensing of VIP and Design IP — typically per-project or perpetual licenses, with royalties tied to chip volume for the Design IP controller family. The second is design services — SoC/ASIC/FPGA design, FPGA development, board design, and firmware development — sold to customers who need turnkey block delivery or full-chip execution. Sales motion is direct to semiconductor OEMs, storage and networking system houses, and FPGA end-users. Named customers include Honeywell, Gennum, Marvell, Broadcom, Panasonic, Agilent, Sierra Logic, Data Transit, and references to the "world's largest storage company" and the "world's largest USB Hub manufacturer," pointing to a mix of marquee and mid-tier accounts across storage, connectivity, and embedded segments.

The company sits inside the EDA ecosystem through interoperability relationships with Mentor Graphics, Synopsys, and Cadence (the three dominant simulator vendors), an FPGA partnership with Xilinx, and standards-body participation in the Serial ATA Working Group. Its competitive position is that of a focused, protocol-broad niche IP vendor rather than a generalist EDA player — competing on depth of protocol coverage and on tape-out-proven engineering rather than on integrated tool-suite breadth. Customer count appears diversified at the logo level, but the absence of revenue disclosure makes concentration at the dollar level unobservable.

Name

Perfectus Technology Inc

Legal name

Perfectus Technology Inc.

Website

https://perfectus.com

Company type

Private

Founded year

2003

Operating status

Operating

Headcount range

51–100 employees

Short description

Perfectus Technology Inc is a US-headquartered semiconductor IP vendor selling SystemVerilog-based Verification IP and Design IP, plus SoC/ASIC/FPGA design services, to chip and SoC customers across connectivity, storage, and serial-interconnect markets.

Ownership category

akta.pro rank

Product category

Semiconductor IP

NAICS

Computer Systems Design and Related Services (54151), Semiconductor and Other Electronic Component Manufacturing (33441)

SIC

Semiconductors & Related Devices (3674), Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Verification IP (VIP) & Protocol Compliance Suites (HDAHAFAG)

akta.pro secondary industries

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF), Custom & Application-Specific ASIC Design Services (HDAHABAJ)

Keywords

• Verification IP
• Semiconductor IP
• SystemVerilog VIP
• ASIC design services
• Chip design services

Headquarters

HQ city

Santa Clara

HQ country

United States

HQ region

North America

Offices4 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales, Infrastructure

Revenue model

1. Verification IP Licensing: Licensing of Genie verification IP products including SATA, SAS, USB, PCIe, Ethernet, Fibre Channel, ONFi, SPI, AMBA, OCP, and SMBus verification IP. Customers receive evaluation licenses and full product licenses for protocol compliance testing.
2. ASIC/SOC/FPGA Design Services: Professional services revenue from full-service SOC and ASIC design engagements, FPGA development, board design, and firmware/software development. Services span from concept to product including architecture, logic design, verification, physical design, and silicon validation.

Go-to-market motion2 records

Distribution channels3 records

Marketing channels4 records

Core offering

Perfectus Technology Inc develops and licenses Verification IP (VIP) and Design IP products for semiconductor chip design under the Genie brand, covering high-speed serial protocols (USB 2.0/3.0, PCIe, SATA, SAS, Fibre Channel, Ethernet, SPI 4.2, ONFi) and bus protocols (AMBA AXI/AHB/APB, OCP, SMBus), built on SystemVerilog/OVM methodologies with proprietary compliance test suites. The company also delivers full-service SOC, ASIC, and FPGA design services from architecture and RTL coding through physical design, DFT, board design, and firmware/software development, serving Fortune 500 semiconductor firms down to startups.

Product overview

Perfectus Technology Inc offers a comprehensive portfolio of Verification IP (VIP) and Design IP products for the semiconductor and chip design industry. The Verification IP portfolio includes Genie-SSU (USB 3.0), Genie-USB (USB 2.0), Genie-PCIe, Genie-SATA, Genie-SAS, Genie-FC (Fibre Channel), Genie-Ethernet, Genie-AMBA (AXI/AHB/APB), Genie-SPI 4.2, SMBUS Verification IP, Genie-ONFi, and OCP Verification IP. The Design IP portfolio includes FBDIMM Controller Core, SAS Expander Core, SATA Controller Core, AMB Core, OCP Master/Slave Controller, and SMBUS Master Controller. These products are complemented by service offerings including SOC/ASIC/FPGA Concept to Product development, FPGA Development, Board Design & Development, and Firmware/Application Software Development. The company's tagline is 'Design Fast. Verify Faster!' and they serve customers including major semiconductor and storage companies.

Differentiator

Problem solved

Functional benefit

Brands

• Genie-PCIe: System Verilog implementation of PCI Express Standards
• Genie-SATA
• Genie-SAS
• Genie-FC
• Genie-USB
• Genie-SSU
• Genie-PCIe (Gen 2)
• Genie-ONFi
• Genie-AMBA
• Genie-SPI 4.2
• Genie-Ethernet
• Genie-SMBus

Products and services

• Genie-SSU (Super Speed USB 3.0) Verification IP SystemVerilog-based verification IP compliant with Super Speed USB 3.0 specifications, supporting host and device configurations with protocol checking, automatic LTSSM handling, link training, isochronous timestamp packets, power management states (U1, U2, U3), and error injection at all layers. Used by Gennum and the world's largest USB Hub manufacturer.
• Genie-USB Verification IP (USB 2.0) SystemVerilog verification IP for USB 2.0 designs supporting Full/High/Low speed modes with UTMI, D+/-, and ULPI interfaces.
• Genie-PCIe Verification IP SystemVerilog implementation of PCI Express standards compliant with v1.0a, v1.1, and v2.0, configurable as Root Complex or Endpoint with link widths x1-x32, full LTSSM, and PCI-SIG compliance tests.
• Genie-PCIe 3.0 Verification IP PCI Express 3.0 verification IP for Gen 3 PCIe designs.
• Genie-SATA Verification IP Verification engine providing complete functional verification framework for SATA-based Host and Target designs, including compliance test suite with more than 200 tests supporting SATA-I, SATA-II, NCQ, Port Selector, and Port Multiplier. Used by Honeywell, Marvell, Panasonic, Agilent, and the world's largest storage company.
• Genie-SAS Verification IP Verification engine for SAS-1.1 and SAS-2 protocol-based designs including initiators, targets, and expander devices, with more than 200 tests and link speeds of 1.5G, 3G, and 6G with wide port support. Used by Marvell, Broadcom, Agilent, Data Transit, and the world's largest storage company.
• Genie-FC (Fibre Channel) Verification IP Fibre Channel verification IP implementing the complete FCP2 stack (FC1 to FC4 layers) for driving FC packets and responding to FC traffic at the application layer. Used by Honeywell and Sierra Logic.
• Genie-Ethernet Verification IP OVM implementation of IEEE Standard 802.3 for Ethernet verification supporting MII and GMII interfaces with multiple language interface options.
• Genie-AMBA AXI Verification IP Verification IP for AMBA 3.0 AXI protocol providing verification engine, bus functional models, and compliance test suites.
• Genie-AMBA AHB Verification IP Verification IP for AMBA AHB protocol providing verification engine, bus functional models, and compliance test suites.
• Genie-AMBA APB Verification IP Verification IP for AMBA APB protocol providing verification engine, bus functional models, and compliance test suites.
• Genie-SPI 4.2 Verification IP Verification IP solution for SPI 4.2 designs compliant to OIF-SPI4-02.0 System Packet Interface Level 4 Phase 2 standard with configurable data path width (32/64/128 bits), N asymmetric ports, calendar lengths up to 1024, and dynamic bit de-skew, supporting PHY and MAC layers.
• SMBus Verification IP Verification IP for SMBus 2.0 specification providing verification engine with SystemVerilog assertions, master/slave configurations, and protocol checking.
• Genie-ONFi Verification IP OVM 2.0-based verification IP fully compliant to ONFi 2.1 specifications for verifying NAND Flash Device designs with up to 4 target devices, 16-bit bus width, source synchronous and asynchronous modes, and interleaving operations.
• OCP Verification IP Bus-independent interface verification IP between IP cores that reduces design time, design risk, and manufacturing costs for SOC designs.
• FBDIMM Controller Core Design IP core compliant with FBDIMM Architecture and Protocol (Rev 0.1a), supporting DDR2 memories up to DDR2-800 with peak bandwidth of 12.8 GB/s, 2 FBDIMM channels (expandable to 4), and dynamic scheduling and interleaving.
• SAS Expander Core Design IP core supporting automatic selection of SAS or SATA hard disk drives with flexible 6-port device configuration and speed negotiation.
• SATA Controller Core SATA Controller Core SAPIS Version 0.9 compliant with NCQ support, port multiplier support, and PCI-X host interface.
• AMB (Advanced Memory Buffer) Core Design IP core supporting intelligent channel initialization, FBDIMM channel error detection, and SMBus interface for configuration registers.
• OCP Master/Slave Controller Core OCP (Open Core Protocol) Master/Slave Controller Core for bus-independent interface between IP cores.
• SMBus Master Controller SMBus Master Controller compliant to SMBus 2.0 specifications with multi-master support, arbitration, and programmable retry buffer.
• SOC/ASIC/FPGA Concept to Product Design Services Full-service SOC and ASIC design support from customer specification to GDSII with full verification, covering architecture, RTL coding, design verification, physical design, circuit design, and DFT for multi-million gate complex designs.
• FPGA Development Services FPGA design services covering RTL coding (Verilog/VHDL), functional and gate-level verification, synthesis, timing analysis, place and route, configuration file generation, and FPGA design conversion.
• Board Design & Development Services Board development services including board specification and design, prototype board development, board manufacturing and testing, and in-board silicon verification.
• Firmware and Application Software Development Services Firmware development services including firmware development, device drivers, RTOS, C modeling, BIOS extension, and ROM development.

Quantifiable outcome

• Verification IP products adopted by world's largest storage company and USB Hub manufacturer
• +2 more outcomes

Named customers10 records

Segments3 records

Ideal customer profiles2 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature8 records

Partnerships

Five partnerships are on record, tiered core.

• Mentor Graphics (Questa Vanguard Program)coreTechnology or IntegrationPerfectus is a partner of Questa Vanguard Program (QVP) of Mentor Graphics which provides breadth of design and verification technologies through partnerships with industry-leading companies. The program brings design and verification engineers world-class product integrations and interoperability to enhance Questa verification options and build a comprehensive SystemVerilog ecosystem.
• Synopsys (SystemVerilog Catalyst Program)coreTechnology or IntegrationPerfectus is a member of Synopsys' SystemVerilog Catalyst program which promotes the development and use of EDA tools, verification IP, and training services which support the SystemVerilog standard language for design and verification.
• Cadence (Verification Alliance Program)coreTechnology or IntegrationPerfectus is a member of Cadence Verification Alliance Program which is a network of expert providers of services, training, and IP development that support Cadence verification solutions. Partners help Cadence customers accelerate adoption of new technologies and improve verification team productivity.
• Xilinx (Alliance Program)coreTechnology or IntegrationPerfectus is a partner of Xilinx Alliance Program which assures the best available total solutions combining Xilinx programmable logic with key technologies from Alliance Program members including IP cores, EDA, DSP and embedded development tools, design services, board-level products, integrated circuits, and electronic components.
• Serial ATA Working GroupcoreStrategic or Co-development PartnerPerfectus is a member of the Serial ATA Working Group which defines, develops and delivers the industry specification for the Serial ATA interface. As a member of the Serial ATA 1.0 and Serial ATA 2.0 Working Groups, Perfectus participates in reciprocal, royalty-free licensing arrangement for compliant portions relating to the SATA 1.0 and SATA II Specifications.

Scale indicators2 records

Recent moves6 records

Expansion highlights4 records

Broad incumbents

• Synopsys: Synopsys is the largest Verification IP vendor through its Verification IP family (VIP, DesignWare interface IP) and bundles VIP with its VCS simulator and full EDA stack. Direct product overlap with Perfectus' Genie-SATA/PCIe/USB/AMBA/SAS VIPs but at vastly larger scale.
• Siemens EDA (formerly Mentor Graphics): Mentor's Questa verification platform includes its own VIP portfolio (Mentor VIP) covering PCIe, USB, AMBA, SATA, and DDR protocols. Perfectus is itself a Questa Vanguard Program partner, while Mentor competes as a VIP vendor on the same engagements.
• Cadence Design Systems: Cadence offers Verification IP (Cadence Verification IP / Perspec) and design IP cores spanning the same high-speed serial protocols (PCIe, USB, SATA, SAS, Ethernet, DDR). Direct competitor through Cadence Verification Alliance program in which Perfectus is also a member.
• Imagination Technologies: Imagination licenses GPU, CPU, and a growing portfolio of connectivity/interface IP cores (PCIe, USB, Ethernet) that compete with Perfectus' Design IP (FBDIMM, SATA, SAS Expander, OCP) rather than its VIP. Operates under a similar IP-licensing business model.

Emerging players

• Aldec: Aldec provides Riviera-PRO simulation and offers its own verification IP family targeting FPGA and ASIC verification flows. Partial product overlap with Perfectus' Genie VIP and FPGA design services offerings.
• VeriSilicon: VeriSilicon is a China-headquartered IP platform offering interface IP (USB, PCIe, DDR, MIPI, HDMI) and full SoC design services, competing directly with both Perfectus' Design IP cores and SOC/ASIC/FPGA design services on geographically overlapping customer segments.

Direct peers

• Truechip Solutions: Truechip Solutions is an India-headquartered VIP specialist providing SystemVerilog/UVM/OVM verification IP for protocols such as DDR, USB, PCIe, SATA, AMBA, and MIPI. Direct competitor in the same niche with overlapping India delivery model.
• Mobiveil: Mobiveil provides semiconductor IP for storage and connectivity protocols (NVM Express, SATA, SAS, DDR, PCIe) plus IP customization services. Closely comparable to Perfectus' storage-controller-focused Design IP (SATA Controller, SAS Expander, FBDIMM, AMB) and SOC design services.
• SmartDV Technologies: SmartDV is a VIP-focused company offering verification IP across more than 60 protocols (PCIe, USB, SATA, SAS, Ethernet, AMBA, DDR, MIPI). Closest peer in business model and product breadth to Perfectus, also operating from US/India engineering centers.
• Avery Design Systems: Avery Design Systems is a pure-play Verification IP company specializing in PCIe, CXL, UCIe, DDR, HBM, AMBA/AXI, USB, SATA, and networking protocols; it competes head-to-head with Perfectus' Genie VIP products on the same protocol compliance and BFM/assertion feature set.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat4 records

Key risks7 records

Key highlights7 records

Customer concentration

• LinkedInlinkedin.com/company/perfectus

Revenue estimate

Valuation estimate

Number of profiles

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Perfectus Technology Inc