Avery Design Systems
- Company typePrivate
- Founded1999
- HeadquartersTewksbury, United States
- Headcount11–50
- GTM typeB2B
- OfferingSoftware
Avery Design Systems firmographics
Firmographics- Name
- Avery Design Systems
- Website
- https://avery-design.com
- Company type
- Private
- Founded year
- 1999
- Operating status
- Operating
- Headcount range
- 11–50 employees
- Ownership category
- akta.pro rank
Avery Design Systems industry classification
Industry- Product category
- Semiconductor Verification IP
- akta.pro primary industry
- Verification IP (VIP) & Protocol Compliance Suites (HDAHAFAG)
- akta.pro secondary industry
- EDA Software Platforms (Digital Implementation, Verification & Signoff) (HDAHAFAA)
Keywords
Where Avery Design Systems is headquartered
LocationHeadquarters
- HQ city
- Tewksbury
- HQ country
- United States
- HQ region
- North America
Markets served
Avery Design Systems business model
Business model- GTM type
- B2B
- Offering type
- Software
- Cost components
- Personnel, Technology or R&D, Marketing or Sales, Operations
Revenue model
- Verification IP Licensing: License-based revenue from Avery Verification IP products sold through Siemens' Questa One platform. Products include protocol VIPs, memory models, compliance test suites, and in-circuit simulation tools for semiconductor verification.
Pricing tiers
| Model | Billing | Price |
|---|---|---|
| Subscription | Annual | Enterprise licensing |
Go-to-market motion1 record
Distribution channels1 record
Marketing channels4 records
Avery Design Systems product offering
Product offeringCore offering
Avery Design Systems develops and licenses Verification IP (VIP) products used by semiconductor engineering teams to verify SoCs, chiplets, and advanced package designs. Its VIP portfolio covers protocols including UCIe, CXL, PCIe, HBM, DDR, and CCIX, and includes simulation VIP, formal/assisted VIP, protocol checkers, coverage, debug, and pre-built compliance test suites aimed at protocol compliance workflows.
Product overview
Avery Design Systems offers the Avery Verification IP (VIP) portfolio, a comprehensive suite of reusable protocol and methodology components integrated under Siemens' Questa One platform. The offering encompasses a broad range of verification IP products organized into three main categories: high-performance compute protocols (CXL, NVMe, PCIe, Ethernet), memory models (DDR, HBM, Flash), and SoC protocols (AMBA, Embedded Storage, Mobile Protocols, USB, Automotive, Multimedia, SSD-HDD Storage, Control/Serial Buses). Additionally, the portfolio includes Avery In-Circuit Simulation for co-verification of RTL hardware and firmware/software layers. The VIP portfolio supports 60+ standard protocols, 5+ industry-exclusive VIPs, and 20+ compliance test suites.
Differentiator
Problem solved
Functional benefit
Products and services
- Verification IP (VIP) for UCIe VIP supporting the Universal Chiplet Interconnect Express (UCIe) standard for pre-silicon functional and compliance verification of chiplet-to-chiplet interconnects. Targeted at semiconductor teams building chiplet and advanced-package designs.
- Verification IP (VIP) for CXL VIP for the Compute Express Link (CXL) protocol, supporting simulation and compliance verification of CXL-based memory and interconnect designs in SoCs. Used by semiconductor and system design teams verifying cache-coherent architectures.
- Verification IP (VIP) for PCI Express (PCIe) Mature VIP for PCI Express used in pre-silicon verification of PCIe-based SoC and system designs. Includes built-in protocol checks, coverage, debug, and compliance test suites.
- Verification IP (VIP) for HBM VIP for High Bandwidth Memory (HBM) interconnect used to verify memory controller and PHY designs in advanced semiconductor products. Aimed at SoC and memory subsystem verification engineers.
- Verification IP (VIP) for DDR VIP for DDR memory standards, providing simulation, protocol checks and coverage for DDR-based memory subsystems in SoC designs.
- Verification IP (VIP) for CCIX VIP for the Cache Coherent Interconnect for Accelerators (CCIX) protocol, supporting verification of coherent interconnects between processors and accelerators. Targeted at SoC teams using heterogeneous compute architectures.
- Compliance Test Suites Pre-built compliance test suites bundled with Avery VIP that enable chip teams to run protocol compliance checks during pre-silicon verification, reducing manual test development.
Quantifiable outcome
- Dramatic verification productivity improvements
- +1 more outcomes
Companies that use Avery Design Systems
Customer profileSegments1 record
Ideal customer profiles1 record
Avery Design Systems technology and API
TechnologyTechnology focussed Yes
API detail
- Has API
- No
- API docs
- API detail
Core technology
AI maturity
App detail
Feature7 records
Avery Design Systems partnerships and signals
Strategic signalPartnerships
One partnership is on record.
- SiemenscoreSiemens distributes and sells Avery Verification IP products through its Questa One platform. Avery VIP is integrated into Siemens' IC verification portfolio as a core component of their protocol verification offerings, with products rebranded as 'Questa One Avery Verification IP'.
Scale indicators3 records
Recent moves1 record
Expansion highlights5 records
Avery Design Systems competitors and assessment
Company assessmentDirect peers
- Synopsys Verification IP (DesignWare): Synopsys is the largest provider of protocol Verification IP through its DesignWare portfolio, directly competing with Avery across CXL, PCIe, DDR, USB, MIPI and many other protocols. Both target SoC design teams seeking off-the-shelf BFMs and compliance suites — the same customer base, the same product category.
- Aldec (Riviera-PRO VIP): Aldec bundles its own VIP offerings with the Riviera-PRO simulator for SoC verification, competing with Avery on protocols like AXI/AMBA, PCIe and memory. Both serve customers looking for simulator-agnostic or simulator-bundled verification IP for chip design.
- Cadence Verification IP: Cadence offers a broad VIP catalog integrated with its Xcelium simulator, directly competing with Avery across PCIe, CXL, memory, automotive and AMBA protocols. Both companies sell reusable protocol verification components to enterprise SoC verification teams through direct EDA sales motions.
Emerging players
- Truechip: Truechip is a niche VIP provider specializing in protocol compliance and verification IP for memory, storage and connectivity standards. It overlaps with Avery's DDR/HBM/Flash/SSD-HDD storage portfolio and competes for the same verification tooling budget at chip companies.
- AMIQ EDA (DVT): AMIQ provides design and verification tools (DVT Eclipse plugin) used by the same SoC verification engineers Avery targets; complementary but adjacent, with overlap in verification methodology tooling and SystemVerilog/UVM workflows.
- Imperas Software: Imperas provides processor and SoC verification IP (notably RISC-V and architectural reference models). It overlaps with Avery's processor-protocol coverage (e.g., AMBA/AXI/CHI) and serves a similar chip-design verification buyer.
- Breker Verification Systems: Breker focuses on system-level, cache-coherent verification — particularly for multi-die and chiplet designs where Avery's UCIe VIP also plays. Both compete for verification budget on emerging heterogeneous SoC architectures, with complementary but overlapping coverage.
Broad incumbents
- Siemens EDA (Questa Verification Platform): Siemens EDA is Avery's parent platform (Questa One) and also sells overlapping VIP directly within its broader verification suite. As a broad incumbent, it has the most comparable distribution reach and bundles simulation, debugging and VIP into enterprise EDA deals.
Market position
Strengths5 records
Weaknesses5 records
Competitive moat4 records
Key risks5 records
Key highlights6 records
Customer concentration
Avery Design Systems social profiles
Digital presenceAvery Design Systems financial estimates
Financial estimateRevenue estimate
Valuation estimate
Avery Design Systems leadership team
Management profileNumber of profiles
Avery Design Systems funding detail
Funding detailFunding overview
Funding rounds
Investors
Funding detail is available on the Subscription and Enterprise plan.Contact sales →
Avery Design Systems M&A and investment
M&A and investmentM&A
Investments
M&A and investment is available on the Subscription and Enterprise plan.Contact sales →
Frequently asked questions about Avery Design Systems
What does Avery Design Systems do?
Avery Design Systems develops and licenses Verification IP (VIP) products used by semiconductor engineering teams to verify SoCs, chiplets, and advanced package designs. Its VIP portfolio covers protocols including UCIe, CXL, PCIe, HBM, DDR, and CCIX, and includes simulation VIP, formal/assisted VIP, protocol checkers, coverage, debug, and pre-built compliance test suites aimed at protocol compliance workflows.
Is Avery Design Systems a public or private company?
Avery Design Systems is a private company. It is classified as corporate owned and is currently operating.
When was Avery Design Systems founded?
Avery Design Systems was founded in 1999. It employs 11 to 50 people.
Where is Avery Design Systems based?
Avery Design Systems is headquartered in Tewksbury, United States, in the North America region.
How does Avery Design Systems make money?
One revenue line is on record: verification IP Licensing.
Who are Avery Design Systems's main competitors?
Direct peers on record are Synopsys Verification IP (DesignWare), Aldec (Riviera-PRO VIP) and Cadence Verification IP. Emerging players are Truechip, AMIQ EDA (DVT), Imperas Software and Breker Verification Systems. Siemens EDA (Questa Verification Platform) is listed as a broad incumbent.
Does Avery Design Systems have an API?
No public API is recorded for Avery Design Systems.
What industry is Avery Design Systems in?
Avery Design Systems's product category is Semiconductor Verification IP. Its primary akta.pro industry code is HDAHAFAG, Verification IP (VIP) & Protocol Compliance Suites, with a secondary code of HDAHAFAA, EDA Software Platforms (Digital Implementation, Verification & Signoff).