What STATS ChipPAC does

STATS ChipPAC is a Singapore-headquartered semiconductor back-end manufacturing and technology services provider operating as a wholly-owned subsidiary of JCET Group (Jiangsu Changjiang Electronics Technology Co., Ltd.). Founded in 1972, the company employs 10,000+ staff across 20+ operational locations, with manufacturing concentrated in Singapore and Incheon, South Korea (SCK and SCK+), and customer-facing offices in the United States (Milpitas, CA) and Switzerland (Préverenges). Its service portfolio spans the full back-end value chain — package integration design and characterization, wafer probing, wafer bumping, package assembly, final testing, and global drop shipment — delivered through a direct enterprise sales model targeting semiconductor IDMs, fabless companies, and automotive OEMs.

The company's technology platform covers the major packaging families: wirebond (QFN, QFP, WB-BGA, WB-LGA), flip chip (fcCSP, fcBGA, C2W, 3DIC), wafer-level packaging (FIWLP, FOWLP), system-in-package (SiP) with EMI shielding and laser-assisted bonding, MEMS and sensor packaging, power device packaging, and 2.5D/3D integration. The flagship differentiator is the proprietary XDFOI high-density fan-out chiplet platform, which is in stable mass production for 2D, 2.5D, and 3D HPC and AI computing integration. CTO Il Kwon Shim holds more than 350 granted patents worldwide covering SiP, flip chip, wafer-level, and 3D integration technologies.

Revenue is generated through long-term, quote-based turnkey service contracts with major semiconductor and automotive customers across five primary verticals: Automotive (ADAS, electrification, in-vehicle computing), Computing (HPC, AI accelerators, networking), Memory (NAND Flash, DRAM — with partnerships among the world's top three memory OEMs), AI Edge (5G RF, AiP, connectivity), and Power & Energy (SiC/GaN, AIGC power modules, analog). The customer base is anchored by long-cycle qualifications, IATF 16949 automotive certification, and an extensive compliance stack (ISO 9001/14001/45001/22301/27001, RBA VAP, Samsung Eco Partner, EU RoHS/REACH). The company holds long-standing partnerships with the top three global memory manufacturers and is a flagship participant in imec's Automotive Chiplet Program alongside GlobalFoundries, Infineon, Silicon Box, and TIER IV. Pricing is not publicly disclosed and engagements are tailored to volume and technology specifications.

Name

STATS ChipPAC

Legal name

STATS ChipPAC Management Pte. Ltd.

Website

https://statschippac.com

Company type

Private

Founded year

1972

Operating status

Operating

Headcount range

5,001–10,000 employees

Short description

STATS ChipPAC is a Singapore-headquartered global OSAT provider and JCET subsidiary offering turnkey semiconductor back-end manufacturing — design, wafer bumping, assembly, test, and drop shipment — across wirebond, flip chip, wafer-level, SiP, and 2.5D/3D packaging for automotive, computing, memory, AI edge, and power customers.

Ownership category

akta.pro rank

Product category

Semiconductor Packaging & Test Services

NAICS

Semiconductor and Related Device Manufacturing (334413)

SIC

Semiconductors & Related Devices (3674)

akta.pro primary industry

Assembly & Packaging Services (Wirebond/Flip-Chip/FCBGA) (HDAHADAA)

akta.pro secondary industry

Advanced Packaging (2.5D/3D-IC, Fan-Out WLP, Chiplets) (HDAHADAB)

Keywords

• Semiconductor packaging services
• Wafer level packaging
• Flip chip packaging
• System-in-package solutions
• Integrated circuit testing

Headquarters

HQ city

Singapore

HQ country

Singapore

HQ region

Asia

Offices4 records

Markets served

GTM type

B2B

Offering type

Hardware or Manufacturing

Cost components

Personnel, Operations, Infrastructure, Technology or R&D, Supply Chain, Marketing or Sales

Revenue model

1. Turnkey Semiconductor Manufacturing Services: Full-range turnkey services including semiconductor package integration design and characterization, R&D, wafer probing, wafer bumping, package assembly, final testing, and global drop shipment to vendors. Revenue is generated through integrated service fees encompassing design services, wafer processing, assembly, test, and logistics, typically structured as long-term contracts with major semiconductor companies.
2. Test Services: Comprehensive test solutions covering RF, analog, mixed-signal, and digital devices with high-throughput platforms for cost reduction and quality assurance. Includes wafer-level testing, final testing, and system-level testing across global facilities.
3. Advanced Packaging Licensing and Technology Services: Technology licensing and engineering services associated with proprietary packaging platforms such as XDFOI fan-out chiplet platform and SiP solutions, delivered as part of customer co-development engagements.

Go-to-market motion1 record

Distribution channels1 record

Marketing channels4 records

Core offering

STATS ChipPAC provides turnkey semiconductor back-end manufacturing services, including package integration design and characterization, R&D, wafer probing, wafer bumping, package assembly, final testing, and drop shipment. Its core offerings span wirebond, flip chip, wafer-level, 2.5D/3D, fan-out and System-in-Package (SiP) technologies, sold primarily to global semiconductor IDMs, fabless companies, and automotive OEMs across automotive, computing, memory, AI edge, and power & energy applications.

Product overview

STATS ChipPAC is an integrated circuit manufacturing and technology services company offering a comprehensive portfolio of semiconductor backend solutions. The core product suite includes Wirebond Packaging, Flip Chip Packaging, Wafer Bumping, Wafer Level Packaging, System-in-Package (SiP), MEMS and Sensors Packaging, and 2.5/3D Packaging technologies. Key technology platforms include the XDFOI High-Density Fan-Out Chiplet Platform (in mass production for HPC and AI computing) and eWLB technology for automotive applications. These are supported by Turnkey Services covering end-to-end manufacturing from design to delivery, Design Services for package characterization, Test Services for wafer through system-level testing, and Packaging Services using FIWLP, FOWLP, IPD, and TSV technologies. Application-specific solutions span Automotive, Computing, Memory, AI Edge, and Power & Energy sectors.

Differentiator

Problem solved

Functional benefit

Products and services

• Wirebond Packaging Semiconductor assembly technology using wire interconnections to connect chips to substrates, supporting QFN, DFN, QFP, WB-BGA, and WB-LGA formats with gold, copper, silver, and palladium-coated wire materials. Used by automotive, memory, MEMS, mobile and power semiconductor customers.
• Flip Chip Packaging Direct die-to-substrate connection technology using solder bumps that reduces parasitics, improves thermal efficiency and shrinks form factors. Supports fcCSP, fcBGA, C2W, and 3DIC formats for large single-die packages, compact modules, and AiP designs.
• Wafer Bumping Foundational process technology providing high-density interconnects directly at wafer level. Supports 200mm and 300mm wafers with redistribution and full turnkey support for flip chip and wafer-level packaging, using printed bump, ball drop, and plated bumping with lead-free and copper pillar alloys.
• Wafer Level Packaging Advanced packaging technology that integrates functionality directly at the wafer stage, reducing size while improving power, speed, and signal integrity. Key to enabling next-generation devices with performance in compact footprints.
• System-in-Package (SiP) Integration technology combining multiple chips and components into a single compact module for faster processing, higher performance, and more functionality. Supports heterogeneous integration of logic, analog, power, and memory ICs using SMT, wirebond, and flip chip with dual-sided molding, EMI shielding, and laser-assisted bonding.
• MEMS and Sensors Packaging Specialized packaging for micro-electro-mechanical systems and sensors enabling real-time sensing, responsiveness, and control in compact, power-efficient designs. Includes full turnkey development with packaging co-design, simulation, BOM qualification, assembly, testing, and quality assurance.
• 2.5D / 3D Packaging Advanced packaging technology that stacks and interconnects multiple components to maximize functionality and performance through higher density, better performance, and more efficient integration.
• Power Device Packaging Advanced packaging solutions for power and analogue devices designed for high-temperature applications, improving thermal efficiency and electrical reliability with high-volume scalability.
• XDFOI High-Density Fan-Out Chiplet Platform Proprietary high-density fan-out chiplet platform for HPC and AI applications, integrating package assembly and testing across 2D, 2.5D and 3D technologies to enable high-bandwidth, high-efficiency computing systems. Currently in stable mass production.
• eWLB (embedded Wafer Level Ball Grid Array) Fan-out wafer-level packaging technology supporting large form factors up to 12x12mm, used in automotive and high-performance applications with fine line/space dimensions down to 8 microns.
• Test Services Comprehensive testing solutions including wafer probing, stacked die solutions, final test automation, and system-level testing. Offers front-end development, wafer-level testing for bumped wafers and known good die, precision final testing, post-test services, and high-throughput system-level testing.
• Packaging Services Full suite of assembly services using wafer-level technologies including FIWLP, FOWLP, IPD, and TSV for reliable, high-performance, and cost-efficient packaging solutions for consumer electronics, automotive, and IoT industries.
• Design Services Advanced analysis and simulation services for package design and characterization, including thermal analysis, mould flow analysis, mechanical analysis, and electrical analysis. Global characterization teams located in China, Singapore, South Korea and the U.S.
• Turnkey Services End-to-end semiconductor manufacturing solutions from package design through global delivery, encompassing wafer bumping, probing, assembly, testing, and direct drop shipping to customer vendors. Serves automotive, AI, and healthcare industries.
• Automotive Packaging Solutions Cost-effective automotive-grade packaging solutions for MCUs and in-vehicle electronics, including QFP, QFN, copper wire BGA, flip-chip, SiP, and fan-out WLP. Supports fine line/space down to 10 microns, bump pitches of 70 microns, and mass production of power module substrates and interconnects.
• Computing Packaging Solutions Advanced packaging solutions for HPC, CPU, GPU, FPGA, ASIC, and networking applications. Features XDFOI platform, cost-effective 2.5D solutions, ultra high-density bumping, and large-scale flip chip with micro-bumping.
• Memory Packaging Solutions Memory packaging for NAND Flash and DRAM with over 20 years of experience. Supports vertical die-stack technology, ultra-thin chip processing, and high-volume production in partnership with the world's top three memory manufacturers.
• AI Edge Packaging Solutions Advanced packaging for 5G era applications including 2.5D/3D, wafer-level packaging, and SiP solutions with collaborative design, simulation, and automated quality control. Supports RF front-end modules, millimeter-wave antennae AiP, and high-performance 5G components.
• Power and Energy Packaging Solutions Advanced power semiconductor and analog device packaging for modern energy, communication, and compute systems. Supports Kelvin formats (TOLL, TO-263-7, TO-247-4), bottom/top/dual-sided cooling, and advanced interconnects including silver sintering and DBC for SiC/GaN, DrMOS, PoL, and IBC applications.

Quantifiable outcome

• Over 100 billion units successfully shipped for QFP/QFN and copper wire BGA packaging solutions
• +4 more outcomes

Named customers1 record

Segments5 records

Ideal customer profiles5 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature9 records

Partnerships

Three partnerships are on record, tiered core and flagship.

• Singapore Semiconductor Industry Association (SSIA) and Institute of Microelectronics (IME), A*STARcoreStrategic or Co-development Partner · 30 October 2025Distinguished guests from the Singapore Semiconductor Industry Association (SSIA) and the Institute of Microelectronics (IME), A*STAR joined STATS ChipPAC's inaugural Advanced Packaging Developer Conference in Singapore. These partnerships support industry dialogue, cross-disciplinary collaboration, and Singapore's position in the global semiconductor ecosystem.
• Imec (Automotive Chiplet Program)flagshipStrategic or Co-development Partner · 15 October 2025STATS ChipPAC joined imec's Automotive Chiplet Program (ACP) Consortium alongside GlobalFoundries, Infineon, Silicon Box, and TIER IV. The ACP is a pre-competitive research program aimed at accelerating chiplet architecture adoption for automotive applications including ADAS, autonomous driving, and in-vehicle infotainment systems. The collaboration focuses on joint R&D projects, standardization efforts, and sustainable technology initiatives to drive technological breakthroughs benefiting the entire industry and customers.
• Top 3 Global Memory ManufacturersflagshipStrategic or Co-development PartnerSTATS ChipPAC has established partnerships with the world's top three memory manufacturers, collaborating on NAND Flash and DRAM packaging development, die-stack technology, and high-volume production for next-generation storage systems.

Scale indicators7 records

Recent moves6 records

Expansion highlights6 records

Broad incumbents

• JCET Group: JCET Group is STATS ChipPAC's parent and one of China's largest OSATs, offering a comparable portfolio of wirebond, flip chip, wafer-level, and advanced packaging. As parent and competing OSAT, JCET shares technology platforms and competes for the same Chinese and global customers.
• ASE Technology Holding: ASE Technology is the world's largest OSAT provider, offering wirebond, flip chip, wafer-level, SiP, and advanced 2.5D/3D packaging across automotive, computing, memory, and AI. Directly comparable as the dominant incumbent competing with STATS ChipPAC across virtually all product lines and customer segments.
• TSMC (Advanced Packaging Division): TSMC's Advanced Packaging division offers CoWoS, InFO, and SoIC for leading-edge AI, HPC, and mobile customers. While a foundry, TSMC increasingly competes for advanced packaging share (CoWoS for AI accelerators) that overlaps with STATS ChipPAC's XDFOI chiplet roadmap.

Direct peers

• Amkor Technology: Amkor is a leading US-headquartered OSAT specializing in advanced packaging, including flip chip, wafer-level fan-out, SiP, and 2.5D/3D for automotive, computing, and communications end markets. Closely comparable to STATS ChipPAC on technology portfolio and customer base, particularly in automotive advanced packaging.
• Tianshui Huatian Technology: Tianshui Huatian is a China-headquartered OSAT offering wirebond, flip chip, and advanced packaging for memory, logic, and consumer customers. Directly comparable as a mid-to-large OSAT competing in mainstream and advanced packaging segments.
• ChipMOS Technologies: ChipMOS is a Taiwan-based OSAT with strong memory packaging, test, and driver IC packaging capabilities serving the same memory and display driver customer base as STATS ChipPAC. Comparable in memory packaging and test services focus.
• UTAC Holdings: UTAC is a Singapore-headquartered OSAT offering analog, mixed-signal, and advanced packaging, with prior CTO Il Kwon Shim as Group CTO before joining STATS ChipPAC. Comparable in OSAT scale, technology breadth, and Singapore/Asia footprint.
• Powertech Technology: Powertech Technology (PTI) is a Taiwan-based OSAT with strengths in memory packaging, flip chip, and advanced packaging for DRAM, NAND, and logic customers. Directly competes with STATS ChipPAC for memory packaging share with major memory OEMs.

Regional players

• Hana Microelectronics: Hana Microelectronics is a Thailand-headquartered OSAT offering IC assembly and test services, with growing advanced packaging capabilities. Comparable in OSAT service model, though it primarily serves different regional customers and a somewhat less advanced technology mix.

Emerging players

• King Yuan Electronics (KYEC): KYEC is the world's largest pure-play semiconductor test service provider, specializing in wafer probing and final test. Comparable as a complementary player in the backend test segment where STATS ChipPAC also competes, though KYEC's model is test-only.

Market position

Weaknesses4 records

Competitive moat6 records

Key risks6 records

Key highlights6 records

Customer concentration

• LinkedInlinkedin.com/company/stats-chippac
• Xx.com/statschippacltd
• Facebookfacebook.com/statschippac

Compliance10 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles11 records

Subsidiaries5 records

Funding overview

Funding rounds1 record

Investors1 record

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about STATS ChipPAC