What MINRES Technologies does

MINRES Technologies GmbH is a privately held German engineering company founded in Munich in 2012 that provides design methodology, productivity IP, tools, and design IP for System-on-Chip (SoC) and embedded system design, with a particular focus on the RISC-V instruction set architecture. The company serves semiconductor companies and embedded system designers across four primary verticals: general semiconductors, automotive electronics (with ISO 26262 considerations), edge computing and IoT, and defense and security. Its core product portfolio centers on The Good Folk Series (TGFS), a generator-based family of silicon-proven RISC-V processor cores (TGC, available in five configurations from RV32 to RV64 with 3-5 stage pipelines), a configurable subsystem called Moonlight built around TGC cores, and a machine learning accelerator (TGA) for edge AI workloads.

The company's second core platform is RAVEN, a hybrid simulation tool launched in 2023 that accelerates SystemC simulations through coarse-grained parallelization and enables co-simulation of SystemC and RTL mapped onto FPGA, with on-premise and AWS Cloud deployment. Supporting tools include the TGC-VP virtual platform, the SCViewer waveform and transaction viewer, and the open-source SystemC Components Library (SCC) providing modeling primitives and bus protocol adapters. The company also offers virtual prototyping professional services covering SoC modeling, architectural exploration, performance analysis, verification automation, and training, backed by ISO 9001 certification and ISO 26262 certifiability for its IP.

MINRES operates as a B2B enterprise field sales organization with no public pricing, multi-year contracts, and direct engagement with engineering teams at customer organizations. Distribution is exclusively direct, supplemented by community-led engagement through technical blogs, RISC-V International strategic membership (since 2017), Embedded4You network membership (since 2018), open-source GitHub repositories, and presentations at industry conferences such as RISC-V Summit Europe and DVCon Europe. The company is founder-owned (Eyck Jentzsch and Wolf-Ekkehard Matzke) with no disclosed external institutional investment, a team of approximately 15 members, and a strategic research footprint through the Scale4Edge consortium with Robert Bosch, Fraunhofer IESE, and multiple German universities.

Name

MINRES Technologies

Legal name

MINRES Technologies GmbH

Website

https://minres.com

Company type

Private

Founded year

2012

Operating status

Operating

Headcount range

11–50 employees

Ownership category

akta.pro rank

Product category

Semiconductor Design IP and EDA Tools

NAICS

Computer Systems Design and Related Services (5415), Other Computer Related Services (541519), Computer Systems Design and Related Services (54151)

SIC

Services-Computer Programming Services (7371), Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

Compute & Acceleration ICs (CPU/GPU/AI/FPGA/ASIC) (HDAHABAC)

akta.pro secondary industries

AI/Neural Processing Units (NPUs) & ML Accelerators (HDAHAJAF), Real-Time & Industrial Control Processors (RT MCUs/PLC-class SoCs) (HDAHAJAL)

Keywords

• RISC-V processor IP
• SoC virtual prototyping
• SystemC simulation tools
• Hybrid FPGA simulation
• Embedded design IP

Headquarters

HQ city

Munich

HQ country

Germany

HQ region

Europe

Offices1 record

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Marketing or Sales, Infrastructure, Operations

Revenue model

1. Design IP Licensing: Licensing of proprietary RISC-V processor cores (TGC family), subsystems (Moonlight), and accelerators (TGA). Generator-based approach allows customization for specific customer requirements.
2. Tools and Productivity Software: Sale or licensing of EDA tools including RAVEN hybrid simulation platform, TGC-VP virtual platform, and SCViewer.
3. Virtual Prototyping Services: Consulting and engineering services for embedded system modeling, architectural exploration, performance analysis, and VP methodology implementation. Includes training and knowledge transfer.
4. Cloud Simulation: RAVEN supports cloud-based hybrid simulation on AWS, providing scalable simulation environments as a managed service.

Pricing tiers

Go-to-market motion3 records

Distribution channels3 records

Marketing channels5 records

Core offering

MINRES Technologies provides silicon-proven, generator-based RISC-V processor IP and configurable subsystems (The Good Folk Series: TGC cores, Moonlight subsystem, TGA ML accelerator) along with the RAVEN hybrid simulation platform for accelerated SystemC/FPGA co-simulation. The company also delivers open-source SystemC modeling tools (SCC, SCViewer, TGC-VP) and professional virtual prototyping services for SoC and embedded system design teams.

Product overview

MINRES Technologies offers The Good Folk Series (TGFS), a unified portfolio of generator-based, flexible hardware IP built around RISC-V architecture. The series comprises three building blocks: The Good Cores (TGC) - five configurable RISC-V processor cores ranging from tiny controllers to application processors; Moonlight - a configurable subsystem providing memories, interconnects and peripherals around TGC; and The Good Accelerator (TGA) - a machine learning accelerator for Edge AI. Alongside the hardware IP, MINRES provides RAVEN, a hybrid simulation platform for accelerating SystemC simulations with FPGA co-simulation and cloud support. Developer resources include TGC-VP virtual platforms, SCViewer waveform analysis tool, and the open-source SystemC Components Library (SCC) for modeling primitives. MINRES also offers professional services spanning virtual prototyping, performance analysis, verification, and training.

Differentiator

Problem solved

Functional benefit

Brands

• The Good Folk Series: A growing family of trustworthy, generator-based and flexible hardware IP, including RISC-V processor cores (TGC), the Moonlight subsystem, and The Good Accelerator (TGA).
• RAVEN
• TGC (The Good Cores)
• Moonlight

Products and services

• The Good Folk Series (TGFS) A family of trustworthy, generator-based and flexible hardware IP designed for low-power Edge/IoT and embedded SoC applications. EDA-vendor agnostic implementation enables integration into customer tool flows.
• The Good Cores (TGC) A family of five flexible, scalable RISC-V processor cores optimized for low-power Edge/IoT applications, featuring optional cache, branch prediction, and trace/debug capabilities. Designed for best performance per watt.
• Moonlight A configurable and extendable subsystem built around a TGC core, providing memories, interconnect infrastructure, and peripherals/controllers. Used as a housekeeping system for larger SoCs handling boot setup, configuration, and peripheral provision.
• The Good Accelerator (TGA) A generator-based machine learning accelerator IP block that offloads demanding deep neural network functions from the CPU. Loosely coupled to work with any processor for Edge AI/Machine Learning workloads.
• RAVEN Hybrid simulation platform that accelerates SystemC simulations through coarse-grained parallelization and enables co-simulation of SystemC and RTL mapped onto FPGA. Supports on-premise and AWS Cloud deployment with automated hardware/software component generation via RavenDSL.
• TGC-VP Virtual Platform Virtual platform built around TGC cores providing ISS, interrupt controllers (plic/clic), GPIO, QSPI, UART terminal and other peripherals. Serves as a starting point for building RISC-V based virtual platform systems.
• SCViewer Transaction trace and VCD waveform viewer tool supporting VCD files (compressed/uncompressed), real numbers, analog waveform display, and SCV transaction recordings in various formats. Available as standalone or Eclipse plugin.
• SystemC Components Library (SCC) Open-source SystemC modeling primitives and blocks including extended logging, config file readers, automatic tracers, TLM2 socket tracing, optimized transaction recording databases, and pin-level adapters for APB, AHB, AXI/ACE, OBI bus protocols.
• Virtual Prototyping Services Strategic engineering services including VP modeling for early software development and architectural exploration, performance-aware simulation environments, customized performance analysis utilities, IP integration, automation of regression testing and CI pipelines, and comprehensive training programs.

Named customers1 record

Segments4 records

Ideal customer profiles2 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration7 records

Feature6 records

Partnerships

15 partnerships are on record, tiered core, strategic, major, supporting and partner.

• RISC-V InternationalcoreStrategic or Co-development PartnerMINRES joined RISC-V Foundation (now RISC-V International) in 2017 as a member. Actively contributes to RISC-V ecosystem development and standards.
• Embedded4YoucoreStrategic or Co-development PartnerMINRES joined the Embedded4You network in 2018, an ecosystem network for embedded technologies.
• ArterisstrategicTechnology or IntegrationCollaboration on SoC modeling and architectural exploration. Presented joint tutorial at DVCon Europe 2025 on efficient SoC modeling using TLM2-based IPs.
• Fraunhofer IESEstrategicStrategic or Co-development PartnerCollaboration on SoC modeling and architectural exploration. Fraunhofer contributed to DVCon Europe 2025 tutorial alongside MINRES and Arteris.
• TU DarmstadtmajorStrategic or Co-development PartnerAdvancing CoreDSL for ISA-level modeling and building infrastructure for integrating ISA extensions. Also collaborated on MANNHEIM-FlexKI project for AI hardware platform integration.
• University of BremenmajorStrategic or Co-development PartnerIntegrating formal methods into virtual platforms, particularly concolic testing, within the Scale4Edge project ecosystem.
• RPTU University Kaiserslautern-LandaumajorStrategic or Co-development PartnerCollaborated on analyzing TGC core for side-channel vulnerabilities within the Scale4Edge ecosystem.
• University of TübingenmajorStrategic or Co-development PartnerDeveloping and presenting demonstrations including ASIC tapeouts within Scale4Edge project. Collaborated on MANNHEIM-FlexKI project top-level design for tape-out.
• Paderborn UniversitymajorStrategic or Co-development PartnerPartner in Scale4Edge project, collaborating on demonstrations and ASIC tapeouts.
• Robert Bosch GmbHmajorStrategic or Co-development PartnerScale4Edge project partner collaborating on demonstrations and ASIC tapeouts.
• GreensocsstrategicTechnology or IntegrationCo-developed QBox solution for embedding QEMU into SystemC virtual platforms. Qualcomm Innovation Center also contributed to QBox project.
• Qualcomm Innovation Center (QuIC)strategicTechnology or IntegrationCo-developed QBox solution for embedding QEMU into SystemC virtual platforms alongside Greensocs.
• AscendosupportingImplementation/ SI/ Consulting PartnerProvided ISO 9001 certification consulting support to MINRES, helping interpret standards and avoid implementation pitfalls.
• AccemicpartnerTechnology or IntegrationPartner company shown in MINRES customer and partner logos section. Collaboration on debug and trace solutions.
• Johannes Kepler University Linz (JKU)majorStrategic or Co-development PartnerCollaboration with WAL (Waveform Analysis Language) team at JKU ICS for automated waveform analysis in RTL verification.

Scale indicators5 records

Recent moves11 records

Expansion highlights6 records

Direct peers

• Codasip: RISC-V processor IP vendor emphasizing customizable cores and Studio tools; competes head-to-head with MINRES in the configurable RISC-V core and embedded segments.
• Andes Technology: Taiwan-based RISC-V CPU IP vendor with broad adoption in IoT and edge applications; overlaps MINRES' Edge/IoT and embedded vertical targets.
• Arteris: Network-on-chip and SoC IP company that co-presented with MINRES at DVCon Europe 2025; competes in adjacent SoC IP categories and is a partner in TLM2-based modeling.
• SiFive: The leading independent RISC-V IP vendor offering RISC-V cores, subsystems, and developer boards; most directly comparable competitor to MINRES' TGC and Moonlight offerings.

Emerging players

• OpenHW Group: RISC-V International-aligned organization driving open-source CORE-V processor IP; competes philosophically with MINRES' commercial RISC-V cores by offering a free alternative.
• Accemic: Embedded debug and trace IP vendor shown as a MINRES partner/customer logo; comparable as a small European embedded IP specialist targeting similar SoC design teams.
• GreenSocs: Open-source SystemC modeling and QEMU-integration specialist; co-developed QBox with MINRES and Qualcomm, and operates in the same virtual prototyping ecosystem.

Broad incumbents

• Cadence (Tensilica): EDA incumbent with the Tensilica customizable processor IP line and full verification/synthesis stack; competes with MINRES in configurable DSP/CPU IP for SoC designs.
• Imagination Technologies: IP vendor offering CPU, GPU, and NPU cores for SoCs; overlaps MINRES in accelerator IP (TGA) and embedded CPU/microcontroller categories.
• Synopsys (ARC processors): Major EDA vendor offering the ARC processor IP family and broad SoC design toolchains; serves the same semiconductor design customers but with a much wider portfolio.

Market position

Strengths4 records

Weaknesses4 records

Competitive moat5 records

Key risks5 records

Key highlights6 records

Customer concentration

• LinkedInlinkedin.com/company/minres-technologies-gmbh

Compliance2 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles2 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about MINRES Technologies