What Sarcina Technology does

Sarcina Technology LLC is a privately held semiconductor packaging and testing services company founded in 2011 and headquartered in Palo Alto, California, with a design and supply chain management office in Taipei, Taiwan. It delivers end-to-end, turnkey services under its branded WIPO (Wafer-in, Product-out) model, spanning package design, wafer bumping and sort, test hardware design (probe cards, loadboards, sockets), power and signal integrity simulation, substrate and assembly management, JEDEC/AEC-Q100 qualification, final test, and production logistics. The company's technology portfolio spans standard packages (flip-chip BGA, wirebond BGA, QFN) and advanced packages (2.5D silicon interposer, 3D stacking, MCM/Chiplet, photonic IC, automotive, and bump pitch transformer / FOCoS-CL), complemented by bi-directional channel simulation for LPDDR5X/DDR5/GDDR6, 112G SerDes, PCIe-6, and 32G UCIe-A/S interfaces.

Sarcina primarily serves AI accelerator and HPC semiconductor companies (nearly 90% of packages are AI-related), alongside networking, ASIC/IP, photonics, automotive, and biomedical customers. Notable customers include Broadcom, Marvell, NXP, Google, Juniper, Cadence, ZTE, H3C, a tier-1 high-speed data communications company, AI startups, and U.S. universities/research centers/hospitals. The company operates a B2B consultative, project-based sales model with multi-year, custom-priced engagements, and reaches customers directly as well as through ecosystem partnerships with Intel Foundry Services (IFS Accelerator Design Services Alliance, January 2024), Keysight Technologies (PathWave ADS simulation), and ASE (FOCoS-CL assembly). Its leadership, including founder and CEO Larry Zu (formerly of Bell Labs, DEC, Intel, and TSMC with ~1,000 career tape-outs and >99% first-time success) and Technical Director Julia Lin, anchors the company's claimed 100% first-time silicon success track record across 100+ package tape-outs.

Name

Sarcina Technology

Legal name

Sarcina Technology LLC

Website

https://sarcinatech.com

Company type

Private

Founded year

2011

Operating status

Operating

Headcount range

1–10 employees

Short description

Sarcina Technology is a boutique semiconductor packaging and testing firm offering turnkey WIPO (Wafer-in, Product-out) services, advanced chiplet/UCIe design, and AI-focused packaging IP to AI accelerator, HPC, networking, and ASIC companies globally.

Ownership category

akta.pro rank

Product category

Semiconductor Packaging Services

NAICS

Semiconductor and Other Electronic Component Manufacturing (33441)

SIC

Services-Commercial Physical & Biological Research (8731), Services-Testing Laboratories (8734)

akta.pro primary industry

Advanced Packaging (2.5D/3D-IC, Fan-Out WLP, Chiplets) (HDAHADAB)

akta.pro secondary industries

Outsourced Semiconductor Manufacturing Services (Back-End EMS/Turnkey) (HDAHADAJ), Test Services (Wafer Sort, Final Test, Burn-In) (HDAHADAD)

Keywords

• Semiconductor packaging services
• Advanced chip packaging
• Wafer testing services
• Chiplet interconnect design
• High performance computing packaging

Headquarters

HQ city

Palo Alto

HQ country

United States

HQ region

North America

Offices2 records

Markets served

GTM type

B2B

Offering type

Services

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales

Revenue model

1. Packaging Services: Package design, substrate fabrication, package assembly, and related engineering services. Covers the entire packaging lifecycle from concept to production-ready packages.
2. Testing Services: One-stop testing services including test plan development, testing hardware design (probe cards, loadboards, sockets), test program development, wafer sort, and final test production services.
3. Qualification Services: JEDEC-standard qualification services including High Temperature Operating Life (HTOL) testing and package qualification to verify robustness under environmental stresses.
4. Production Services: Full production management including yield enhancement, wafer bumping, wafer sort, assembly, final test, failure analysis, return material authorization, logistics and shipping.
5. Application Specific Advanced Packaging (ASAP) Services: Boutique collaborative experience providing advanced packaging design, test, assembly and production management services tailored to specific product requirements.

Pricing tiers

Go-to-market motion3 records

Distribution channels3 records

Marketing channels8 records

Core offering

Sarcina Technology delivers turnkey AI and high-performance semiconductor packaging and testing services from wafer to finished chip. The company provides package design, power and signal integrity simulation, wafer probing, final test hardware design, and test program development across advanced and standard package types. Operating on a "wafer-in, chip-out" (WIPO) service model, Sarcina manages everything from test design to supply chain logistics for semiconductor, AI, HPC, networking, photonic, and biomedical customers.

Product overview

Sarcina Technology is a semiconductor packaging and testing turnkey company offering the WIPO (Wafer-in, Product-out) integrated service model as its core offering. The WIPO service encompasses design, simulation, assembly, testing, qualification, and production management. The company's technology portfolio includes Advanced Packaging Services (2.5D silicon interposer, 3D stacking, MCM/Chiplet, photonic IC, automotive, bump pitch transformer) and Standard Packaging Services (flip-chip BGA, wirebond BGA, QFN) complemented by Simulation Services (PI/SI channel simulation for SerDes, PCIe, memory interfaces). Key products include the AI Platform for AI-specific packaging, UCIe-A/S Chiplet Interconnects for die-to-die communication, Bump Pitch Transformer technology for cost-effective 2.5D packaging, and Photonic Package Design Solutions for co-packaged optics. Sarcina operates on a 'wafer-in, chip-out' model managing the complete supply chain from test design through delivery.

Differentiator

Problem solved

Functional benefit

Products and services

• WIPO (Wafer-in, Product-out) Integrated Services Comprehensive turnkey service covering wafer bumping, wafer sort, package design, test hardware design, design simulations, substrate and hardware fabrication, chip assembly, final test, IC and package qualification, and production management. Eliminates the need for customers to maintain internal hardware teams for packaging, testing, and production.
• Advanced Packaging Services Includes 2.5D silicon interposer packaging, 3D stacking, MCM/Chiplet implementation, photonic IC packaging, automotive packaging, and bump pitch transformer packaging from microbump to C4 bump for high-performance computing applications.
• Standard Packaging Services Design and implementation of flip-chip BGA, wirebond BGA, and QFN packages enabling quick, convenient, and cost-effective solutions for various ASIC chip applications.
• Simulation Services Comprehensive bi-directional channel simulations including PI/SI for LPDDR5X/DDR5/GDDR6, 112G SerDes, PCIe-6, and 32G UCIe-A/S interfaces with eye diagram analysis to ensure performance before tape-out.
• Testing Services One-stop testing services including test plan development, design and manufacturing of testing hardware (probe cards, loadboards, sockets), test program conversion, and production wafer sort and final test using Teradyne, J750, Catalyst, and Advantest 93K testers.
• Qualification Services JEDEC-standard qualification services including High Temperature Operating Life (HTOL) testing on burn-in-boards and package qualification per JEDEC, AEC-Q100, or customer-specific standards.
• Production Services Full production management including yield enhancement, wafer bumping, wafer sort, assembly, final test, failure analysis, return material authorization, logistics, and shipping.
• AI Platform Advanced AI packaging platform leveraging ASE's Fan-Out Chip-on-Substrate-Chip Last assembly technology with UCIe-A interposer supporting chiplets. Enables cost-effective customizable packaging for AI applications with up to 64-bit data interface per module, 32 GT/s transmission speed, LPDDR5X/6 and HBM options, package sizes up to 100mm x 100mm, and power specs up to 500W forced air or 1000W liquid cooling.
• UCIe-A/S Chiplet Interconnect IP Patented die-to-die interconnect IP for chiplet-based architectures supporting data rates up to 32 GT/s with scalable bandwidth configurations from 16 to 256 bits and beyond. Fully compliant with UCIe 2.0 standard, targeting high-performance computing, AI, data centers, and networking.
• Bump Pitch Transformer (BPT) Silicon bridge technology replacing expensive silicon TSV interposers with cost-effective redistribution layers (RDL). Ideal for homogenous and heterogenous chiplet integration targeting HPC devices for AI, data center, microprocessor, and networking applications.
• Photonic Package Design Solutions Photonic IC packaging solutions for Co-Packaged Optics (CPO) enabling high data rate, high bandwidth, and low power interconnects. Includes silicon photonics co-design, opto-electronic interface engineering, multi-chip module layout, and precision optical coupling.

Named customers11 records

Segments6 records

Ideal customer profiles6 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

AI capability1 record

Feature9 records

Scale indicators8 records

Recent moves6 records

Expansion highlights5 records

Others

• Teradyne: Leading ATE supplier (including J750 and Catalyst testers cited by Sarcina) used by Sarcina in its testing services; primarily an equipment supplier to Sarcina's WIPO service, with overlapping exposure to AI semiconductor test demand.
• Keysight Technologies: Test and measurement/EDA vendor whose PathWave ADS simulation platform Sarcina uses for PI/SI analysis; a stated partnership/ecosystem enabler rather than direct competitor, but Keysight's own design services arm overlaps with Sarcina's simulation offering.

Direct peers

• Amkor Technology: One of the world's largest OSATs providing advanced packaging (2.5D, 3D, fan-out, chiplet integration) and test services to semiconductor and AI customers; directly comparable to Sarcina's WIPO turnkey packaging and test model.
• Powertech Technology (PTI): Taiwan-based OSAT providing advanced packaging and test services including wafer-level packaging and 2.5D/3D integration; competes with Sarcina's advanced packaging offerings for AI/HPC and networking customers.
• ASE Technology Holding: Largest global OSAT offering advanced packaging including FOCoS-CL, 2.5D/3D, and chiplet integration; Sarcina explicitly uses ASE's FOCoS-CL assembly technology in its AI Platform, making ASE both a partner and the most direct competitor for advanced packaging services.
• JCET (Jiangsu Changjiang Electronics Technology): Leading Chinese OSAT providing advanced packaging, wafer sort, and final test services for AI, automotive, and communications customers; competes with Sarcina in turnkey back-end semiconductor services globally.

Broad incumbents

• Synopsys: EDA leader offering chip-package-board co-design tools (3DIC Compiler) and IP for advanced packaging including UCIe PHY; provides complementary technology to Sarcina's packaging design services and competes for design services wallet share at hyperscaler/AI customers.
• Intel Foundry (Advanced Packaging): Intel's foundry business offers EMIB, Foveros, and other advanced packaging technologies; Sarcina is a member of Intel Foundry Services (IFS) Accelerator Design Services Alliance, making Intel both partner and competitor for advanced packaging services.
• TSMC (Advanced Packaging): Leading foundry offering industry-leading advanced packaging platforms (CoWoS, InFO, SoIC) for AI/HPC customers; competes with Sarcina in 2.5D/3D and chiplet packaging, though Sarcina also partners with TSMC indirectly through Larry Zu's prior tenure.

Emerging players

• Deca Technologies: Specialist in fan-out wafer-level packaging (FOWLP) and adaptive patterning, providing advanced packaging IP and services for chiplet integration; comparable to Sarcina's Bump Pitch Transformer and chiplet-focused advanced packaging offerings.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

• LinkedInlinkedin.com/company/sarcina-technology-llc

Revenue estimate

Valuation estimate

Number of profiles

Profiles3 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Sarcina Technology