SignatureIP

What SignatureIP does

SignatureIP is a privately held semiconductor IP company founded in 2021 and headquartered in Milpitas, California, that develops silicon infrastructure IP and chiplet design services for advanced system-on-chip (SoC) and chiplet-based designs. The company's portfolio spans 30+ licensable IP blocks across four categories — interconnect (Coherent NoC and Non-coherent NoC compliant with CHI Rev E.b and AXI4, plus IOMMU, system-level cache, and protocol bridges), interface (PCIe Gen 6 Subsystem with PCI-SIG certification at 32 GT/s non-flit mode achieved September 2025, and CXL 3.0 Subsystem with memory pooling and back-invalidation), SysWare integration IP (DMA, boot, eFUSE, PVT, debug), and SoC peripherals (SPI, I2C, UART, GPIO). All blocks are microarchitected from first principles for power-performance-area optimization, with ATC/ATS/DTI pre-integrated across PCIe Gen 6 and CXL 3.0 for single-attachment NoC connectivity. SignatureIP also operates iNoCulator, a cloud-native browser-based NoC EDA tool that generates latency- and throughput-optimal coherent and non-coherent NoC topology and synthesizable RTL directly from architectural targets.

Name

SignatureIP

Legal name

SignatureIP Corporation

Website

https://signatureip.ai

Company type

Private

Founded year

2021

Operating status

Operating

Headcount range

11–50 employees

Short description

SignatureIP develops and licenses silicon infrastructure IP — including PCI-SIG-certified PCIe Gen 6, CXL 3.0, and CHI-compliant NoC blocks — and delivers custom Compute, IO, and Memory Expander chiplet design services to fabless semiconductor companies and hyperscalers building AI accelerators, RISC-V processors, and HPC systems.

Ownership category

akta.pro rank

Product category

Semiconductor IP

NAICS

Semiconductor and Related Device Manufacturing (334413), Semiconductor and Other Electronic Component Manufacturing (3344)

SIC

Semiconductors & Related Devices (3674)

akta.pro primary industry

Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH)

akta.pro secondary industry

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF)

Keywords

• Semiconductor IP licensing
• Network-on-chip design
• PCIe Gen 6 controller
• CXL 3.0 subsystem
• Chiplet design services

Headquarters

HQ city

Milpitas

HQ country

United States

HQ region

North America

Offices4 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Operations, Marketing or Sales, Infrastructure

Revenue model

1. Standalone IP Licensing: Customers license individual verified RTL IP blocks from the 30+ block portfolio. Each block is available standalone for integration into the customer's own SoC. Licensing is transaction-based, with potential per-unit royalty components. Delivery is within days to weeks. The same IP blocks are also used inside chiplet design engagements.
2. Chiplet Design Engagements: Custom design services where SignatureIP assembles IP blocks into Compute, IO, or Memory Expander silicon tailored to the customer's specification. This is a professional services model with milestone-based delivery from SystemC Model through Silicon Prototype. Engagements include full design and verification flow (simulation, FPGA prototype, emulation, physical implementation).
3. Per-Unit Royalties: Embedded in chiplet design engagements and potentially in standalone IP licenses — customers pay royalties based on silicon units shipped using SignatureIP IP.

Go-to-market motion4 records

Distribution channels4 records

Marketing channels6 records

Core offering

SignatureIP develops and licenses silicon infrastructure IP blocks — including PCIe Gen 6 Subsystem, CXL 3.0 Subsystem, coherent and non-coherent Network-on-Chip (NoC) fabric, system-level cache, IOMMU, protocol bridges, SysWare management IP, and SoC peripherals — delivered as verified RTL to fabless semiconductor companies. The company also performs custom chiplet design engagements assembling Compute, IO, and Memory Expander silicon to customer specification, and provides the cloud-native iNoCulator browser-based NoC EDA tool for architectural exploration and RTL generation.

Product overview

SignatureIP is a silicon infrastructure IP platform offering standalone licensable IP blocks (30+ blocks across four categories) plus custom chiplet design engagements. The IP portfolio includes: PCIe Gen 6 Subsystem (PCI-SIG certified) and CXL 3.0 Subsystem for high-speed interfaces; Coherent NoC (C-Noc) and Non-coherent NoC (NC-NOC) for chip interconnect; System-level Cache (L3/SLC), IOMMU, and Protocol Bridges for compute; SysWare (DMA, Boot, eFUSE, PVT, Debug) and SoC Peripherals (SPI, I2C, UART, GPIO) for system management. The platform also includes the cloud-native iNoCulator tool for NoC topology exploration and RTL generation. Custom chiplet design engagements deliver Compute Subsystem (CSS), IO Subsystem (IOSS), and Memory Expander silicon built to customer specification using the same verified IP blocks. ATC, ATS, and DTI are pre-integrated across PCIe Gen 6 and CXL 3.0 subsystems, enabling direct NoC attachment without additional glue logic.

Differentiator

Problem solved

Functional benefit

Brands

• iNoCulator: Cloud-native NoC EDA tool for generating latency-optimal and throughput-optimal C-Noc and NC-NOC topology from browser-based interface.

Products and services

• PCIe Gen 6 Subsystem Clean-sheet PCI-SIG certified PCIe Gen 6 controller IP with ATC, ATS, and DTI pre-integrated; supports RC/EP dual mode, x1–x16 link widths, 1 GHz operating frequency, and PAM4 signaling. Designed for fabless SoC teams integrating high-speed host connectivity.
• CXL 3.0 Subsystem Full CXL 3.0 IP supporting CXL.io, CXL.cache, and CXL.mem protocols with Type 1, Type 2, and Type 3 device support, memory pooling, and back-invalidation. Shares ATC/ATS/DTI architecture with the PCIe Gen 6 Subsystem for single NoC attachment point. Targeted at SoC teams building memory-expansion and disaggregated-memory products.
• Coherent NoC (C-Noc) CHI Rev E.b compliant coherent interconnect backbone for CPU/GPU cores, AI accelerators, and HBM controllers; supports mesh and ring topology options; RTL generated by iNoCulator; Arm- and RISC-V-compatible interfaces. Used by SoC architects building multi-core compute fabrics.
• Non-coherent NoC (NC-NOC) Lightweight non-coherent fabric for IO peripherals, DMA engines, and subsystem controllers; configurable bus widths and topology, AXI4/AXI4-Lite compatible, power-optimized; bridges to C-Noc via CHI-AXI protocol bridge. Targeted at SoC peripheral and IO subsystems.
• System-level Cache (L3 / SLC) Configurable last-level shared cache (4 MB to 32 MB+), N-WAY set-associative, with stash transactions for prefetch flows and integrated proxy cache for IO coherency; CHI compliant and attaches to C-Noc HN-F port. Used in compute SoCs requiring shared cache hierarchies.
• IOMMU Input/Output Memory Management Unit providing two-stage address translation (S1+S2), SMMUv3 architecture compatibility, TLB and page-table walk hardware, fault reporting to hypervisor/OS; integrated directly into NoC slave ports. Targets SoCs requiring secure DMA and memory protection.
• Protocol Bridges Integration glue connecting heterogeneous IP blocks across different bus protocols: CHI-AXI bridge, CHI-CPI bridge (cross-socket CHI), AXI4-SFI bridge (Arm Scalable Fabric Interface); configurable data widths and ID widths. Used by SoCs combining Arm, RISC-V, and custom accelerators.
• SysWare IP System management and integration IP blocks including DMA engine, boot flash controller with DMA, eFUSE OTP controller (APB), PVT sensor interface (APB), AXI4-to-APB3 bridge, debug interface controller, SPI master/slave, I2C master/slave, UART, watchdog timer, GPIO controller, and GP timers. Used by SoC teams requiring management and integration infrastructure.
• SoC Peripherals Board-level I/O and multi-use peripheral controllers including SPI master (4 CS) and slave, I2C master (4) and slave, UART, watchdog timer, GP timers, and GPIO controller. Used by SoC teams assembling peripheral subsystems.
• iNoCulator NoC Design Tool Cloud-native browser-based NoC EDA tool that configures NoC targets (bandwidth, latency, QoS), generates SystemC models for virtual prototyping, and outputs production-ready synthesizable SystemVerilog RTL for both C-Noc and NC-NOC topologies. Used by SoC architects for top-of-funnel exploration before committing to IP licensing.
• Compute Chiplet / Compute Subsystem Design Custom compute silicon design engagement assembling partner RISC-V/CPU cores, SigIP coherent CHI NoC (C-Noc), NC-NOC, IOMMU, system-level cache (SLC/L3), protocol bridges, DMA, SoC peripherals, SysWare, and UCIe D2D interface into a customer-spec compute die. Delivered as a milestone-based professional services engagement from SystemC model through Silicon Prototype.
• IO Chiplet / IO Subsystem Design Custom IO silicon design engagement featuring SigIP PCIe Gen 6 and CXL 3.0 subsystems with pre-integrated ATC/ATS/DTI, partner SerDes/PHY, and partner UCIe D2D interface; PCI-SIG certified at 32 GT/s. Delivered as a milestone-based professional services engagement targeting accelerator cards, NICs, DPUs, and IO chiplet designs.
• Memory Expander Silicon Design Custom CXL 3.0 Type 3 endpoint silicon design engagement implementing memory expander capability using SigIP's CXL 3.0 Subsystem in CXL.mem mode; presents DRAM capacity as Host-managed Device Memory (HDM) to host CPU or AI accelerator; supports DDR5, LPDDR5, and HBM3 via partner memory controller. Delivered as a milestone-based professional services engagement for HPC and AI server memory disaggregation.

Quantifiable outcome

• Lowest-power PCIe Gen 6 on the market (modular power domains, no legacy overhead)
• +4 more outcomes

Segments4 records

Ideal customer profiles4 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration7 records

Feature9 records

Partnerships

Eight partnerships are on record, tiered core.

• Marquee SemiconductorcoreImplementation/ SI/ Consulting PartnerMarquee Semiconductor extends SignatureIP's engineering capacity for custom chiplet design engagements. Provides additional ASIC design, verification, and integration capability across multiple geographies through a validated partner network. Complementary to SigIP's IP and architecture leadership.
• Siemens EDAcoreTechnology or IntegrationSiemens EDA (Questa and Veloce proFPGA) is SignatureIP's sign-off and emulation partner. SignatureIP's design flow uses Siemens Questa for RTL sign-off with pre-configured UVM testbenches and VIP suites, and Siemens Veloce proFPGA CS platform for emulation and PCIe 5.0 PCI-SIG certification runs. PCIe Gen 6 certified on Veloce proFPGA CS hardware.
• Leading RISC-V Core PartnercoreTechnology or IntegrationValidated integration paths with a leading RISC-V processor core partner for the Compute chiplet. SignatureIP provides all fabric, cache, and interface IP; the RISC-V processor core itself is sourced from the partner. This is a deliberate clean-boundary partnership model where each vendor owns their domain.
• Arm CHI EcosystemcoreTechnology or IntegrationSignatureIP's Coherent NoC (C-Noc) is CHI Rev E.b compliant and Arm-compatible. The company participates in the Arm CHI ecosystem with validated integration paths for Arm-based SoC designs using the CHI protocol.
• SerDes / PHY PartnercoreOEM/ Whitelabel/ Licensing PartnerPartner-provided high-speed SerDes/PHY for PCIe Gen 6 and CXL 3.0 physical layer across all three silicon units. Multi-rate (2.5 GT/s through 32 GT/s non-flit mode), PAM4 support, PMA integration with equalization. Process-node portable (TSMC, Samsung, Intel Foundry). Used across PCIe Gen 6, CXL 3.0, and UCIe interfaces.
• UCIe D2D Interface PartnercoreOEM/ Whitelabel/ Licensing PartnerPartner-provided UCIe D2D (Die-to-Die) interface for chip-to-chip connectivity within multi-silicon chiplet packages. UCIe standard-compliant adapter with configurable channel width and speed. Used on all three silicon units (Compute, IO, Memory Expander) for UCIe chip-to-chip links between dies.
• PCI-SIGcoreTechnology or IntegrationPCI-SIG (PCI Special Interest Group) membership. SignatureIP is a PCI-SIG certified integrator: PCIe Gen 5 certified and PCIe Gen 6 32 GT/s non-flit mode certified September 2025. Membership enables participation in PCIe specification development and certification programs.
• CXL ConsortiumcoreTechnology or IntegrationActive member of the CXL Consortium as a spec contributor. SignatureIP's CXL 3.0 Subsystem implements the full CXL.io/CXL.cache/CXL.mem stack and participates in consortium activities for CXL specification development.

Scale indicators9 records

Recent moves6 records

Expansion highlights5 records

Direct peers

• Rambus: Rambus licenses high-speed interface IP including PCIe and CXL controller and PHY subsystems to semiconductor and data center customers. SignatureIP's PCIe Gen 6 and CXL 3.0 subsystems directly overlap with Rambus' interface IP portfolio, and both serve similar fabless and hyperscaler buyers.
• Mobiveil: Mobiveil is a fabless semiconductor IP company offering PCIe, CXL, NoC, and memory controller IP for SoC designs. Mobiveil is a direct peer in the same interface and interconnect IP categories SignatureIP serves, with comparable fabless IP licensing business model.
• Silicon Creations: Silicon Creations is a specialty IP vendor focused on high-performance SerDes/PHY, PLLs, and other mixed-signal IP for advanced process nodes. It is comparable as a focused, fabless IP specialist supplying interface-layer building blocks into the same customer base as SignatureIP.
• Eliyan Corporation: Eliyan develops UCIe-based die-to-die interconnect IP and chiplet enablement technology for multi-die SoC packages. Eliyan competes directly with the chiplet design and UCIe integration portion of SignatureIP's offering and targets the same fabless chiplet customers.
• Arteris: Arteris is the leading independent supplier of Network-on-Chip IP and is the closest direct competitor to SignatureIP's C-Noc, NC-NOC, and system-level cache offerings. Both companies target SoC architects at fabless semiconductor companies and compete on coherent NoC IP quality, configurability, and ecosystem fit.
• Alphawave Semi (Marvell Connectivity): Alphawave Semi is a leading supplier of high-speed connectivity IP including PCIe Gen 5/6 and CXL subsystems and SerDes. Now part of Marvell, it remains a direct competitor in the high-speed interface IP market that SignatureIP targets with its PCIe Gen 6 and CXL 3.0 offerings.

Emerging players

• Astera Labs: Astera Labs designs CXL/PCIe retimer and connectivity silicon for data center and AI infrastructure. While Astera Labs sells its own chips rather than licensing IP, it operates in the same CXL/PCIe ecosystem, engages the same hyperscaler customers, and shapes the demand environment for CXL 3.0 IP suppliers like SignatureIP.
• Baya Systems: Baya Systems is an emerging NoC and fabric IP startup targeting AI accelerator and chiplet SoC designs. It is a newer entrant in the coherent NoC and AI fabric IP category where SignatureIP's C-Noc and iNoCulator tool compete.

Broad incumbents

• Cadence: Cadence offers a broad IP portfolio (PCIe, CXL, memory, interconnect) alongside its EDA and system design tools. Cadence is a broad incumbent that overlaps with SignatureIP across interface IP and system IP but does not specialize in coherent NoC tooling or chiplet design services.
• Synopsys: Synopsys DesignWare is the dominant broad-line semiconductor IP portfolio, including PCIe, CXL, NoC, memory controllers, and security IP, bundled with the company's EDA tools. SignatureIP competes against Synopsys across all four of its IP categories but as a focused specialist against a much larger portfolio vendor.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks5 records

Key highlights7 records

Customer concentration

• LinkedInlinkedin.com/company/signature-ip-corporation
• Xx.com/SignatureIp
• Facebookfacebook.com/profile.php

Compliance3 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles9 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about SignatureIP