What Defacto Technologies does

Defacto Technologies is a French electronic design automation (EDA) software company founded in 2003 by Dr. Chouki Aktouf and headquartered in Grenoble, France. The company builds SoC Compiler, a front-end System-on-Chip integration platform that consolidates RTL, IP-XACT, UPF, SDC, LEF/DEF, and Liberty design formats into a single unified database, exposed through Python, Tcl, C++, Java, Perl, and Ruby APIs. The platform enables synthesis-ready RTL generation, IP integration, multi-view coherency checking, RTL-level DFT signoff, UPF power-intent management, and post-synthesis gate-level optimization. SoC Compiler v11.0 (2025) positions the product as the first front-end SoC Compiler that ingests user specification with building blocks and automatically generates synthesis-ready SoC RTL and design collaterals, including RISC-V subsystem support.

The company serves major semiconductor companies globally — claiming penetration of most of the top 15 worldwide — across communication, processor, AI, IoT, automotive, mobile, and HPC end-markets. Named customers include Socionext, Synapse Design, Atos, OpenFive, Sipearl, ETRI, and Dolphin Design. The ISO26262 certification up to ASIL D (SGS-TÜV, 2022) enables use in automotive functional-safety design flows, and the Arm Partner Catalog listing plus integrated Arm IP Explorer flow anchor ecosystem positioning. Defacto maintains sales and support presence in France, the United States (Palo Alto), Japan, Taiwan, South Korea, Israel, and India (via resellers).

Defacto operates a pure enterprise B2B software model with annual quote-based licensing and 24/7 global support. Headcount is approximately 12-13 (12 in Grenoble plus 1 in Palo Alto), with plans to nearly double to roughly 20 employees via the EmpoSoC project. Revenue is not publicly disclosed. In 2024 the company was awarded a €2.5M European EIC Accelerator grant (against a ~€4.1M total project envelope) to develop AI-driven next-generation EDA software under the EmpoSoC brand, planned for H2 2026 launch. The company remains privately held and founder-led with no disclosed institutional venture capital backing.

Name

Defacto Technologies

Legal name

Defacto Technologies SAS

Website

https://defactotech.com

Company type

Private

Founded year

2003

Operating status

Operating

Headcount range

11–50 employees

Short description

Defacto Technologies provides front-end SoC integration software (SoC Compiler) to major semiconductor companies worldwide. Founded in 2003 in Grenoble, France, the platform enables synthesis-ready RTL generation, IP-XACT, UPF, DFT signoff, and multi-format design integration with ISO26262 automotive certification.

Ownership category

akta.pro rank

Product category

Electronic Design Automation (EDA) Software

NAICS

Software Publishers (5132)

SIC

Services-Prepackaged Software (7372)

akta.pro primary industry

EDA Software Platforms (Digital Implementation, Verification & Signoff) (HDAHAFAA)

akta.pro secondary industries

Verification IP (VIP) & Protocol Compliance Suites (HDAHAFAG), System-Level, Multi-Physics & Package/PCB Co-Design (EDA) (HDAHAFAD), EDA Cloud/SaaS, Design Data Management & Collaboration (HDAHAFAJ)

Keywords

• Chip design software
• RTL design tools
• SoC integration platform
• Electronic design automation
• Front-end EDA

Headquarters

HQ city

Grenoble

HQ country

France

HQ region

Europe

Offices7 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Marketing or Sales, Operations

Revenue model

1. Software Licenses and Subscriptions: Defacto sells EDA software licenses, previously under the STAR brand and now under SoC Compiler. The company serves major semiconductor companies worldwide with annual licensing and support contracts.

Pricing tiers

Go-to-market motion2 records

Distribution channels2 records

Marketing channels5 records

Core offering

Defacto Technologies sells the SoC Compiler, an ISO26262-certified front-end EDA platform that uses a unified persistent database to integrate RTL, IP-XACT, UPF, SDC, LEF/DEF, and Liberty design formats and automates the construction, verification, and signoff of synthesis-ready System-on-Chip RTL. The platform exposes multi-language APIs (Python, Tcl, Perl, C++, Java, Ruby) for RTL editing, IP integration, power management, DFT signoff, connectivity checks, and gate-level optimization, and is complemented by the SoC Planner automated design exploration tool and the EmpoSoC AI-driven EDA project.

Product overview

Defacto Technologies offers SoC Compiler as its core front-end SoC integration platform, previously marketed as STAR RTL Design Platform. The unified solution comprises multiple integrated modules: RTL Design Builder, RTL Design Checker, RTL Design For Test (DFT), RTL Low Power, Padring, RTL IP Integration, and RTL Code Complexity Metrics (CCM). The SoC Compiler platform is complemented by Open APIs and Customization capabilities supporting Python, Tcl, C++, and Java for custom application development. Additional offerings include SoC Planner (automated design exploration and RTL generation with eco-design scoring) and the EmpoSoC EIC Accelerator project. The platform addresses the full pre-synthesis SoC design workflow including RTL integration, power management (UPF), timing constraints (SDC), physical design (LEF/DEF), and IP-XACT handling, with gate-level design optimization available for post-synthesis PPA improvements.

Differentiator

Problem solved

Functional benefit

Brands

• SoC Compiler: Main product platform - a certified ISO26262 RTL design solution for front-end SoC integration, verification and signoff of IP cores and System on Chips. Previously named STAR.
• SoC Planner
• EmpoSoC

Products and services

• SoC Compiler ISO26262-certified, unified front-end SoC integration and signoff platform for enterprise semiconductor teams. Provides a persistent database spanning RTL, IP-XACT, UPF, SDC, LEF/DEF, and Liberty with multi-language APIs for assembling, verifying, and signing off synthesis-ready SoC RTL.
• STAR (Legacy RTL Design Platform) Previous-generation RTL build and signoff platform covering design exploration, editing, and structure verification. Superseded by SoC Compiler but still referenced for modules, customer onboarding, and installed base customers.
• SoC Planner Automated SoC design exploration tool that combines A-DECA technology from CEA, Defacto's RTL stack, and PDM technology from Innova to autonomously explore, score, and generate Pareto-optimal RTL configurations from KPI-driven specifications.
• EmpoSoC EIC Accelerator-funded project delivering the next-generation AI-powered software solution for electronic circuit design automation. Intended to reduce design effort by about 30% versus traditional tools and to extend Defacto's AI Assistant and MCP Server architecture into broader chip-design workflows.
• RTL Code Complexity Metrics (CCM) Standalone complexity analysis product that extracts cyclomatic code complexity metrics across Verilog, VHDL, and SystemVerilog designs, helping RTL teams prevent synthesis and post-synthesis problems by pinpointing critical code regions through the design hierarchy.
• STAR RTL Application Development Environment (ADE) Application development environment for CAD teams to build custom in-house RTL applications and migrate legacy scripts. Exposes multi-API access (Python, Tcl, C++, Java) to RTL build and signoff capabilities through HDL-format-agnostic interfaces.

Quantifiable outcome

• Reduces design cycles from months to days
• +5 more outcomes

Named customers7 records

Segments4 records

Ideal customer profiles2 records

Technology focussed Yes

API detail

Has API

Yes

API docs

API detail

Core technology

AI maturity

App detail

Integration2 records

AI capability4 records

Feature7 records

Partnerships

Four partnerships are on record, tiered core.

• ArmcoreTechnology or Integration · 1 January 2024Joint SoC design flow solution. Arm IP Explorer integrated with SoC Compiler for automated generation of Arm-based SoCs. Defacto listed in Arm Partner Catalog. Developed joint flow for automatic RTL, IP-XACT, UPF generation from Arm architecture.
• CEA (French Research Lab)coreStrategic or Co-development Partner · 1 January 2023Collaborative R&D partnership for SoC Planner project. CEA contributes A-DECA (Automated Design space Exploration for Computing Architectures) technology. Three-year collaborative project funded by BPI France as part of France 2030 program.
• Innova Advanced TechnologiescoreStrategic or Co-development Partner · 1 January 2023Collaborative R&D partnership for SoC Planner project. Innova contributes PDM (Project and Design Management) technology. Part of the three-year collaborative project.
• Accellera Systems InitiativecoreStrategic or Co-development PartnerActive member of Accellera committee for IP-XACT standard definition. Committed to supporting new versions of the standard. Involved in IP-XACT 2021 version development.

Scale indicators12 records

Recent moves6 records

Expansion highlights6 records

Broad incumbents

• Siemens EDA (Mentor Graphics): Siemens EDA delivers full-stack IC design tools including Calibre and Tessent. As one of the 'big three' EDA incumbents, it competes broadly with Defacto across the digital implementation flow.
• Synopsys: Synopsys is the largest EDA incumbent with full-stack digital design tools. Its acquisition of Atrenta shows how majors absorb front-end EDA niches, posing a structural threat to small specialists like Defacto.
• Cadence Design Systems: Cadence is one of the three major EDA incumbents offering a full RTL-to-GDSII suite. Defacto positions itself as complementing (rather than competing head-on with) Cadence flows, and Cadence is listed as a Defacto partner logo.

Direct peers

• Agnisys: Agnisys provides EDA software for IP and SoC design specification, register management, and design automation — directly comparable to Defacto's IP-XACT-driven SoC Compiler platform and serving similar front-end SoC design challenges.
• Blue Pearl Software: Blue Pearl offers RTL design analysis, CDC, and synthesis-checking tools — directly comparable to Defacto's RTL Code Complexity Metrics, structural verification and SoC signoff capabilities at the pre-synthesis stage.
• Concept Engineering: Concept Engineering provides RTL visualization, debugging, and SoC integration tools — overlapping with Defacto's front-end SoC integration, connectivity extraction, and structural verification capabilities.
• Real Intent: Real Intent delivers RTL-level verification and signoff tools (CDC, Lint, Lint-Power) — directly comparable to Defacto's RTL Design Checker, RTL DFT signoff, and UPF coherency checking capabilities.

Emerging players

• MunEDA: MunEDA provides EDA tools for circuit sizing and design centering optimization — partially overlapping with Defacto's design space exploration (SoC Planner) and gate-level PPA optimization capabilities.
• Zero ASIC: Zero ASIC offers configurable chiplet/SoC platforms with EDA tooling for rapid SoC assembly — an emerging player addressing similar SoC integration and assembly pain points that Defacto targets with SoC Compiler.
• Atrenta (acquired by Synopsys): Atrenta was a leading pre-synthesis RTL signoff and IP-XACT-focused EDA vendor acquired by Synopsys in 2015. It serves as the historical analog for what a successful front-end EDA specialist can become — or what happens when it gets absorbed by an incumbent.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks6 records

Key highlights7 records

Customer concentration

• LinkedInlinkedin.com/company/550099

Compliance1 record

Revenue estimate

Valuation estimate

Number of profiles

Profiles6 records

Funding overview

Funding rounds1 record

Investors1 record

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Defacto Technologies