What Accellera does

Accellera Systems Initiative is an independent, not-for-profit membership organization founded in 2000 and headquartered in Elk Grove, California. The organization creates, supports, promotes, and advances system-level design, modeling, and verification standards for the worldwide electronics industry, operating with 11-50 employees. It was formed through a series of consolidations: the 2000 merger of OVI and VHDL International, the 2010 merger with The SPIRIT Consortium, the 2011 merger with the Open SystemC Initiative, and the 2013 acquisition of OCP-IP. Its standards portfolio covers the full EDA and IP design and verification stack, including SystemC (IEEE 1666), SystemVerilog (IEEE 1800), Universal Verification Methodology / UVM (IEEE 1800.2), IP-XACT (IEEE 1685), Portable Test and Stimulus (PSS), Unified Power Format / UPF (IEEE 1801), Verilog-AMS, UVM-MS, SystemRDL, UCIS, OCP, SA-EDI, and the new Clock Domain Crossing standard, with selected standards subsequently formalized through the IEEE Standards Association. Accellera generates revenue primarily through three tiers of annual membership dues (Corporate at $25,000, Associate at $7,500, and Start-up/University at $2,000) supplemented by the global DVCon conference series held in the US, Europe, India, China, Japan, and Taiwan. Its member ecosystem includes all major EDA vendors (Cadence, Siemens EDA, Synopsys) and semiconductor companies (AMD, Arm, Intel, NXP, Qualcomm, ST Microelectronics), with standards reaching more than 200,000 downloads through the IEEE Get Program and 14,800+ members in the UVM LinkedIn community. Governance is provided by a Board of Directors chaired by Lu Dai of Qualcomm, with Lynn Garibaldi serving as Executive Director.

Name

Accellera

Legal name

Accellera Systems Initiative

Website

https://accellera.org

Company type

Private

Founded year

2000

Operating status

Operating

Headcount range

11–50 employees

Short description

Accellera Systems Initiative is a not-for-profit standards organization that develops and promotes EDA and IP standards, including SystemC, SystemVerilog, UVM, and PSS, serving the global semiconductor and electronic design automation industry through member working groups and the DVCon conference series.

Ownership category

akta.pro rank

Product category

Electronic Design Automation Standards

NAICS

Computer Systems Design and Related Services (5415)

SIC

Services-Computer Integrated Systems Design (7373)

akta.pro primary industry

System-Level, Multi-Physics & Package/PCB Co-Design (EDA) (HDAHAFAD)

akta.pro secondary industries

Verification IP (VIP) & Protocol Compliance Suites (HDAHAFAG), Standards Development & Publishing (SDOs, Technical Standards) (MPAJACAB), International Standards, Norms & Technical Regulatory Bodies (BPADAAAJ)

Keywords

• EDA standards development
• Electronic design automation
• System-level verification standards
• IP integration standards
• Hardware design languages

Headquarters

HQ city

Elk Grove

HQ country

United States

HQ region

North America

Offices1 record

Markets served

GTM type

B2B

Offering type

Services

Cost components

Personnel, Operations, Technology or R&D, Marketing or Sales, Infrastructure

Revenue model

1. Membership Dues: Accellera generates revenue through annual membership dues at three tiers: Corporate Members ($25,000/year), Associate Members ($7,500/year), and Start-up/University Members ($2,000/year). Membership is in effect upon receipt of completed agreement and dues, expiring December 31 of each calendar year.

Pricing tiers

Go-to-market motion1 record

Distribution channels4 records

Marketing channels10 records

Core offering

Accellera Systems Initiative develops, maintains, and advances open standards for system-level design, modeling, and verification of electronic systems used by the worldwide electronics industry. Its portfolio includes standards such as SystemC, SystemVerilog, Universal Verification Methodology (UVM), IP-XACT, Portable Test and Stimulus (PSS), Unified Power Format (UPF), Clock Domain Crossing (CDC), and Open Core Protocol (OCP). Standards are contributed to IEEE for formal standardization and are distributed free of charge through the IEEE GET Program, with funding provided by member company dues.

Product overview

Accellera Systems Initiative is a not-for-profit standards development organization that creates, supports, and promotes system-level design, modeling, and verification standards for the worldwide electronics industry. Rather than a single product, Accellera offers a comprehensive portfolio of technical standards and specifications that work together to enable interoperable EDA and IP design workflows. The core standards include IP-XACT for IP reuse and design automation, Universal Verification Methodology (UVM) for verification environment reuse, Portable Test and Stimulus (PSS) for portable verification intent, SystemC for system-level modeling, SystemVerilog for hardware design and verification, and Unified Power Format (UPF) for low-power design. Additional standards cover mixed-signal verification (Verilog-AMS, UVM-MS), register description (SystemRDL), coverage interoperability (UCIS), security assurance (SA-EDI), functional safety, clock domain crossing, and federated simulation. These standards are developed through member company working groups and formalized through partnership with IEEE, with conferences like DVCon (U.S., Europe, India, China, Japan, Taiwan) providing community engagement and knowledge sharing.

Differentiator

Problem solved

Functional benefit

Brands

• DVCon: Design and Verification Conference - a series of technical conferences focused on design and verification of electronic systems held in multiple regions including U.S., Europe, India, China, Japan, and Taiwan.
• Accellera

Products and services

• SystemC A C++ modeling platform for system-level design, including core language, transaction-level modeling (TLM), analog/mixed-signal extensions (AMS), Configuration Control & Inspection (CCI), synthesis, and verification libraries. Used by SoC designers, EDA tool vendors, and embedded software developers.
• SystemVerilog Unified hardware design, specification, and verification language standardized as IEEE 1800, covering design and verification capabilities for electronic systems. For hardware designers and verification engineers.
• Universal Verification Methodology (UVM) Industry-standard verification methodology for reusable verification environments and verification IP, provided as both an API standard and a reference implementation using SystemVerilog. For verification engineers across semiconductor and EDA organizations.
• IP-XACT Standard (IEEE 1685) providing XML schemas and recommended vendor extensions for packaging, integrating, and reusing intellectual property within EDA tool flows, enabling IP reuse and design flow automation. For IP providers, SoC integrators, and EDA tool vendors.
• Portable Test and Stimulus Standard (PSS) Standard for specifying verification intent and behavior that is reusable across target platforms (emulation, silicon, simulation), enabling users to specify behaviors once and derive multiple implementations. For verification teams needing portability across abstraction levels.
• Unified Power Format (UPF) Standard (IEEE 1801) for design and verification of low-power, energy-aware electronic systems. For SoC designers working on power-constrained designs.
• Clock Domain Crossing (CDC/RDC) Standard Standard for IP abstraction for clock and reset domain crossing integration, enabling interoperable and tool-independent CDC/RDC collateral exchange from IP to SoC design flows. For IP providers and SoC integrators requiring vendor-neutral CDC signoff.
• Open Core Protocol (OCP) Common standard for intellectual property core interfaces facilitating plug-and-play System-on-Chip design, providing a universal complete socket standard regardless of on-chip architecture. For IP integrators and SoC designers.
• Verilog-AMS Analog mixed-signal modeling and verification extensions for Verilog, enabling continuous and discrete signal representation in electronic system design. For mixed-signal design and verification engineers.
• UVM Mixed-Signal (UVM-MS) Universal Verification Methodology extensions (UVM-MS 1.0) for mixed-signal verification, enabling UVM-based verification of designs with both analog and digital components.
• SystemRDL Specification for register description language used to describe hardware registers and memory-mapped devices in a standardized format. For hardware and verification engineers.
• Unified Coverage Interoperability Standard (UCIS) Standard for interoperability of coverage data across different EDA tools and verification environments.
• Open Verification Library (OVL) Assertion library providing standard checkers for verifying properties in HDL designs.
• SCE-MI (Standard Co-Emulation Modeling Interface) Standard interface for describing on-chip scan compression and emulation modeling interactions.
• Security Annotation for Electronic Design Integration (SA-EDI) Standard addressing security concerns in IP integration, providing security annotations to identify and mitigate vulnerabilities in SoC/ASIC designs. For IP integrators and security-conscious SoC designers.
• Design & Verification Conference (DVCon) Global conference series providing technical programs, tutorials, exhibitions, and networking focused on design and verification of electronic systems, held in U.S., Europe, India, China, Japan, and Taiwan. For EDA and semiconductor industry professionals.
• Accellera Membership Annual membership in Accellera Systems Initiative available at three tiers: Corporate ($25,000/year), Associate ($7,500/year), and Start-up/University ($2,000/year). Includes working group participation, voting rights (Corporate/Associate), and pre-release access to standards.

Quantifiable outcome

• 200,000+ downloads through IEEE Get Program
• +1 more outcomes

Named customers9 records

Segments4 records

Ideal customer profiles4 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature6 records

Partnerships

One partnership is on record.

• IEEE Standards AssociationflagshipStrategic or Co-development PartnerAccellera's ongoing partnership with IEEE Standards Association formalizes and governs Accellera-developed standards. Standards developed by Accellera are contributed to IEEE for formal standardization and ongoing change control. Through the IEEE Get Program, over 200,000 downloads of Accellera standards have been distributed at no cost to the community. The partnership includes IEC/IEEE Dual Logo Agreements for certain standards.

Scale indicators2 records

Recent moves10 records

Expansion highlights6 records

Direct peers

• IEEE Standards Association: Accellera's flagship partner for formal standardization; ratifies and distributes Accellera-developed standards (e.g., SystemVerilog, UVM, IP-XACT) and runs the IEEE Get Program that has driven 200,000+ downloads of Accellera content. Operates a similar consensus-based SDO model and shares the same member companies.
• JEDEC Solid State Technology Association: Semiconductor engineering standards body covering memory, packaging, and interconnects. Serves the same semiconductor design and manufacturing membership as Accellera and runs a similar committee-based standards development model, though focused on hardware interfaces rather than EDA languages.
• Si2 (Silicon Integration Initiative): Member-funded consortium developing standards for IC design challenges including OpenAccess, power formats, and 3D-IC integration. Comparable in mission (EDA/IP interoperability standards), governance (member-driven SDO), and customer base (same EDA vendors and IDMs).
• Object Management Group (OMG): International SDO responsible for modeling and middleware specifications (UML, SysML, DDS). Same member-funded, working-group-driven model and same enterprise customer base as Accellera, with overlapping interest in system-level modeling standards.
• Khronos Group: Open standards consortium with member-funded governance, board seats from leading technology companies, and royalty-free specifications that get formalized through partner bodies. Directly comparable organizational model to Accellera, applied to graphics, compute, and ML APIs.
• RISC-V International: Open ISA standards organization with a similar member-funded SDO governance model, board representation from leading semiconductor companies, and ratified specifications that move into formal standards bodies. Closely parallel organizational structure to Accellera, applied to processor ISA rather than EDA languages.

Emerging players

• OpenHW Group: Open-source hardware organization developing verified RISC-V processor IP. Uses a similar member-funded, working-group model and overlaps Accellera's IP-XACT/OCP constituency around IP packaging, reuse, and verification.
• CHIPS Alliance: Linux Foundation project hosting open-source silicon designs, EDA tools, and verification frameworks. Comparable community-driven model focused on chip design infrastructure; intersects Accellera's portable stimulus and verification reuse agenda.

Broad incumbents

• Eclipse Foundation: Large open-source foundation hosting working groups across embedded, IoT, and tooling domains. Operates a broader portfolio than Accellera but uses the same member-funded governance model and serves some overlapping tool/vendor constituencies.

Others

• Open SystemC Initiative (historical): Predecessor organization that merged into Accellera in December 2011; functionally a part of Accellera today and maintained only as a historical reference. Mentioned here because the SystemC community portal still operates under the systemc.org domain that OSCI originally established.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks5 records

Key highlights6 records

Customer concentration

• Xx.com/accellera
• GitHubgithub.com/accellera-official
• YouTubeyoutube.com/@accellera
• Facebookfacebook.com/AccelleraSystemsInitiative
• LinkedInlinkedin.com/company/accellera-systems-initiative

Revenue estimate

Valuation estimate

Number of profiles

Profiles9 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about Accellera