SJ Semiconductor Co.

Name

SJ Semiconductor Co.

Legal name

SJ Semiconductor Co.

Website

https://en.sjsemi.com

Company type

Private

Founded year

2014

Operating status

Operating

Headcount range

11–50 employees

Ownership category

akta.pro rank

Product category

Semiconductor Advanced Packaging Foundry

NAICS

Semiconductor and Related Device Manufacturing (334413), Semiconductor and Other Electronic Component Manufacturing (33441)

akta.pro primary industry

Advanced Packaging (2.5D/3D-IC, Fan-Out WLP, Chiplets) (HDAHADAB)

akta.pro secondary industries

Assembly & Packaging Services (Wirebond/Flip-Chip/FCBGA) (HDAHADAA), Foundry Platform & Design Enablement Services (PDK/DFM/Process Qualification) (HDAHACAJ)

Keywords

• Semiconductor packaging services
• Wafer bumping foundry
• 3D multi-die integration
• Wafer level chip scale packaging
• Antenna-in-package technology

Headquarters

HQ city

Jiangyin

HQ country

China

HQ region

Asia

Offices3 records

Markets served

GTM type

B2B

Offering type

Hardware or Manufacturing

Cost components

Infrastructure, Technology or R&D, Personnel, Operations, Supply Chain

Revenue model

1. Advanced Packaging and Testing Services: Full-service advanced packaging and testing for wafer level advanced packaging and multi-die integration processing. Services include wafer bumping, CP testing, WLCSP, RDL fan-out, and 3D multi-die integration. Revenue is generated through manufacturing service fees for these specialized semiconductor manufacturing processes, serving the whole process from bumping/RDL through testing to packaging shipment.
2. Chiplet-based Multi-Chip Packaging: Chiplet-based multi-chip packaging has grown from 5.3% of revenue in 2022 to over 56% by mid-2025, representing a major shift in revenue composition toward higher-value advanced packaging solutions used in smartphones, 5G, HPC, data centers, and automotive electronics.
3. MEOL Foundry Services: Middle-End-Of-Line (MEOL) foundry specializing on advanced Bumping and wafer level packaging, providing one-stop advanced packaging service to global and domestic IC design houses. Services cover 12-inch bumping and wafer testing for smartphones, DRAM, and power management chips.

Go-to-market motion2 records

Distribution channels2 records

Marketing channels3 records

Core offering

SJ Semiconductor Co. (SJSemi) is a Middle-End-Of-Line (MEOL) pure-play foundry providing wafer-level advanced packaging and testing services to global IC design houses. Its core offerings include wafer bumping on 200/300mm wafers, Chip Probing (CP) testing, Wafer Level Chip Scale Packaging (WLCSP), and 3D multi-die integration built on its proprietary SmartPoser™ platform (including SmartAiP™ for 5G mm-Wave and SmartPoser-HD for HPC/AI applications). Services are delivered from its Jiangyin, China headquarters and serve end applications in smartphones, 5G, HPC, AI, data centers, and automotive electronics.

Product overview

SJSemi is a MEOL (Middle-End-Of-Line) pure play foundry providing wafer-level advanced packaging and testing services. The core portfolio consists of Wafer Bumping, CP Testing, WLCSP, and APDP as foundational services, with SmartPoser™ serving as the proprietary technology platform powering advanced 3D Multi-Die Integration solutions. SmartPoser™ derivatives include SmartAiP™ (5G mm-Wave antenna-in-package) and SmartPoser-HD (high-density 3D integration). The company offers full RDL Fan-Out packaging for large chips and is China's only mass producer of silicon-based 2.5D packaging. Services span the full advanced packaging value chain from bumping and wafer testing through 3D integration, targeting applications in smartphones, 5G, HPC, AI, automotive electronics, and data centers.

Differentiator

Problem solved

Functional benefit

Brands

• SmartPoser: A novel, patented 3D multi-chip integration technology platform enabling 3D integration of active and passive devices for lower power delivery loss and higher performance per watt.
• SmartAiP
• SmartPoser-HD

Products and services

• Wafer Bumping Wafer-level advanced packaging service in which bumps are formed upon under bump metallization (UBM) electroplated on die pad openings. Offers lead-free bumps (SnAg) and copper pillar bumps for higher I/O density. Services cover 200mm and 300mm wafer bumping for global IC design houses.
• CP Testing (Chip Probing) Electrical and functional performance testing of chips at wafer level using Automatic Test Equipment (ATE) and probe cards. Covers test program development, probe card maintenance, test hardware design, and total test solution development for Logic SOC, Memory, and Mixed-Signal IC.
• WLCSP (Wafer Level Chip Scale Packaging) Wafer-level chip scale packaging that leverages wafer processes to achieve higher interconnect density, better performance, and lower power consumption in a compact form factor. Provides 200/300mm FI/FO packaging, multiple layer/double side RDL, wafer thinning, saw with ELK laser grooving, and frame form or tape/reel shipping.
• SmartPoser™ 3D Multi-Die Integration Platform Novel patented 3D multi-chip integration platform that enables 3D integration of active and passive devices for lower power delivery loss and higher performance per watt. Key enabling technologies include ultra-high Cu vertical interconnect, multi-layer double-sided fine pitch RDLs, wafer-level multi-layer precise aligned antennas, flip-chip, and SMT. Patented in China and the United States.
• SmartAiP™ 5G mm-Wave Antenna-in-Package Wafer-level antenna-in-package technology derived from the SmartPoser™ platform and designed for 5G mm-Wave applications. Delivers ultra-wideband operation from 24GHz to 43GHz, 12.5 dB ultra-high gain (about 4x existing solutions), handset-friendly <1mm thickness, room for RFFE module integration, and good heat dissipation.
• SmartPoser-HD High Density 3D Chip Integration High density, highly integrated, and ultra-thin 3D chip integration technology derived from the SmartPoser™ platform. Uses high density RDL and vertical interconnect to realize high density 3D integration for high performance package solutions in mobile, HPC, and AI applications.
• Full RDL Fan-Out Packaging for Large Chips Wafer-level full RDL (ReDistribution Layer) fan-out packaging for large chips, enabling substrate-less packaging using multi-layer fine pitch RDL technology. First successful realization in China of replacing traditional substrate packaging with wafer-level fan-out packaging for large-size computing chips.
• APDP (Advanced Package Development) Advanced packaging technology development and R&D services based on the SmartPoser™ technology platform, focused on 3D heterogeneous integration of active and passive devices to achieve high bandwidth, high speed, and low power consumption.
• 3D Multi-Die Integration (Silicon-based 2.5D / Chiplet Packaging) Advanced 3D multi-die integration and silicon-based 2.5D packaging for chiplet production. As of 2024, SJSemi is the only provider capable of mass producing silicon-based 2.5D packaging solutions in mainland China. Includes 3x reticle TSV interposer technology for sub-micron level advanced chip interconnect.

Quantifiable outcome

• Highest revenue growth among global OSATs in 2023 per Yole market research
• +5 more outcomes

Named customers2 records

Segments3 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Feature6 records

Partnerships

Four partnerships are on record, tiered core.

• NANO LABScoreTechnology or Integration · 1 August 2022Strategic partnership for mass production of wafer-level full RDL Fan-Out packaging for large chips. NANO LABS and SJSemi cooperated to implement multi-layer fine pitch RDL technology, achieving mass production of large-size full RDL package structure (Cuckoo 2 chip, 800mm² bare die, finished products up to 1600mm²) for near-memory computing chip.
• Speed Wireless Technology Co., Ltd.coreTechnology or Integration · 1 March 2019SJSemi collaborated with Speed Wireless Technology to develop and demonstrate SmartAiP™ 5G mm-Wave technology. Speed Wireless provided outstanding designed antenna and transceiver, enabling the low power loss advantage and ultra-wideband solution demonstration for 5G mm-Wave commercialization.
• SMIC (Semiconductor Manufacturing International Corporation)coreStrategic or Co-development Partner · 1 August 2014SJSemi was founded in 2014 through a strategic alliance between SMIC and JCET. SMIC is China's leading pure-play semiconductor foundry. The company was later completely transferred from SMIC and JCET following 2021 board meeting.
• JCET (Jiangsu Changjiang Electronics Technology Co., Ltd.)coreStrategic or Co-development Partner · 1 August 2014SJSemi was founded in 2014 through a strategic alliance between SMIC and JCET. JCET is a leading OSAT provider. The company was later completely transferred from SMIC and JCET following 2021 board meeting.

Scale indicators13 records

Recent moves7 records

Expansion highlights6 records

Broad incumbents

• Samsung Foundry (Samsung Electronics): Provides advanced packaging including I-Cube (2.5D) and X-Cube (3D) for HPC and AI applications. A broad incumbent competing for the same advanced packaging wallet as SJSemi.
• Intel Foundry (IFS): Intel's foundry services include advanced packaging offerings (Foveros 3D, EMIB 2.5D) that compete for the same HPC, AI, and chiplet customer volumes SJSemi is targeting through SmartPoser-HD and silicon interposer solutions.
• TSMC (Advanced Packaging / 3DFabric): TSMC's 3DFabric (CoWoS, InFO, SoIC) is the global benchmark for 2.5D/3D advanced packaging. It is a broader incumbent but directly competes for chiplet, HPC, and AI customer packaging volumes that SJSemi is targeting.

Direct peers

• ASE Technology Holding: World's largest OSAT offering bumping, WLCSP, flip-chip, and advanced packaging including FOCoS and TSV-based solutions. Directly comparable business model and customer base to SJSemi across smartphones, 5G, and HPC.
• JCET Group (Jiangsu Changjiang Electronics Technology): China's largest OSAT and a founding strategic partner of SJSemi (alongside SMIC). Offers bumping, WLCSP, flip-chip BGA, and 2.5D/3D packaging, directly competing for Chinese advanced packaging customers.
• Amkor Technology: Second-largest global OSAT with leading advanced packaging capacity, including silicon interposer-based 2.5D solutions (S-LINE) for HPC and AI chips. Directly comparable in chiplet and advanced packaging services.
• Tianshui Huatian Technology (Huatian Technology): Major Chinese OSAT offering a wide range of packaging and test services including advanced bumping and fan-out. Competes with SJSemi in mainland China for IC design house packaging volumes.
• ChipMOS Technologies: Taiwan-based OSAT providing bumping, WLCSP, and final test services. Comparable in offering and customer profile to SJSemi's CP testing and wafer-level packaging services.
• Tongfu Microelectronics (TFME): Top-tier Chinese OSAT providing bumping, WLCSP, flip-chip, and advanced packaging to global and domestic IC design houses. A domestic direct competitor in 12-inch bumping and WLCSP where SJSemi is market leader.
• Powertech Technology (PTI): Taiwan-based OSAT specializing in DRAM/power management IC packaging and bumping. Comparable in MEOL bumping and wafer-level packaging services, particularly for memory and logic IC customers.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat6 records

Key risks6 records

Key highlights7 records

Customer concentration

Compliance8 records

Revenue estimate

Valuation estimate

Number of profiles

Profiles7 records

Funding overview

Funding rounds2 records

Investors1 record

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about SJ Semiconductor Co.