What True Circuits, Inc. does

True Circuits, Inc. is a privately held semiconductor intellectual-property company founded in 2002 and headquartered in Sunnyvale, California, with an additional design center in Milan, Italy. The company develops, markets, and licenses a focused portfolio of analog/mixed-signal IP for chip designers — primarily phase-locked loops (PLLs), delay-locked loops (DLLs), and DDR physical interface (PHY) hard macros — supported by an open electronic-design automation platform called JDE (JSPICE Design Environment). Core technology is built around a proprietary self-biased PLL/DLL architecture, analog delay-line DLL design, and a digital control algorithm in the Ultra+ family; products span six PLL categories (Ultra+, IoT, General Purpose, Clock Generator, Spread Spectrum, Deskew), multiple DLL variants (DDR DLL, Multi-Phase DLL, synthesizable Micro DLL), and a DFI 5.1-compliant DDR PHY supporting LPDDR5, DDR4, LPDDR4, DDR3, and LPDDR3, with silicon-proven availability from 180nm down to 4nm across TSMC, GlobalFoundries, and UMC.

The company sells through a multi-channel model: direct licensing to fabless semiconductor companies and ASIC/SoC designers, distribution partnerships with Arm, Rambus, ChipEstimate, and Design & Reuse, and the True Partner Program with approximately ten of the world's largest ASIC design services firms (including ADTechnology, Alchip, Faraday, GUC, VeriSilicon, HCLTech, Toppan, and Tessolve). Revenue is generated through one-time perpetual IP licensing without royalties, supplemented by design and integration services; pricing is not publicly disclosed and is gated behind an NDA process. Customers span many of the world's leading semiconductor, systems, and electronics companies — disclosed logos include Renesas, Arm, Tsinghua University, Canaan Creative, SiFlower, and Icera — across telecommunications, IoT/wearables, mobile, automotive, HPC, AI, and cloud compute end markets.

The business is founder-led and entirely self-owned by its co-founders (Stephen Maneatis as CEO and Aldo Bottelli as VP of Engineering / chief technologist), with no disclosed institutional investment, external fundraising, or parent company. The organization is intentionally small (11–50 employees), composed of highly qualified analog/mixed-signal engineers with advanced degrees, and reinvests in product development through a regular cadence of new PLL/DLL lines and incremental platform features. Strategic posture emphasizes technical depth in timing, deep foundry relationships, and partner-led distribution over scale or geographic breadth.

Name

True Circuits, Inc.

Legal name

True Circuits, Inc.

Website

https://truecircuits.com

Company type

Private

Founded year

2002

Operating status

Operating

Headcount range

11–50 employees

Short description

True Circuits, Inc. licenses analog/mixed-signal semiconductor IP — primarily PLLs, DLLs, and DDR PHYs — to fabless semiconductor and ASIC/SoC designers worldwide, with products silicon-proven from 180nm to 4nm across TSMC, GlobalFoundries, and UMC, and supported by an open EDA platform (JDE/JSPICE).

Ownership category

akta.pro rank

Product category

Semiconductor IP

NAICS

Semiconductor and Other Electronic Component Manufacturing (3344)

SIC

Semiconductors & Related Devices (3674)

akta.pro primary industry

Hardware/Chip Design IP Cores (Processor, Interface, Analog, Security) (HDAHAFAF)

akta.pro secondary industries

IP Enablement, Characterization & Porting Services (HDAHAFAI), Silicon IP Subsystems & Chiplet IP (Die-to-Die, UCIe, NoC, I/O chiplets) (HDAHAFAH)

Keywords

• Semiconductor IP licensing
• Phase-locked loop IP
• Delay-locked loop IP
• DDR PHY IP
• Mixed-signal circuit design

Headquarters

HQ city

Los Altos

HQ country

United States

HQ region

North America

Offices2 records

Markets served

GTM type

B2B

Offering type

Software

Cost components

Personnel, Technology or R&D, Supply Chain, Operations, Marketing or Sales

Revenue model

1. IP Licensing: TCI licenses its PLL, DLL and DDR PHY IP directly to customers. Licensing terms are very attractive and do not require royalty payments. Customers license hard macros and receive design kits including specifications, user guidelines, behavioral simulation models, timing synthesis models, layout abstracts, complete layout (GDSII), and LVS netlist.
2. Design and Integration Services: TCI provides design and integration services for customers requiring additional support in integrating and customizing PLL, DLL and DDR PHY IP for their specific applications.
3. Indirect Sales through Partners: Partnerships with other semiconductor companies provide indirect sales channels for licensed products. This includes IP distribution partners, design services partners, and the True Partner Program with major ASIC design services companies.

Pricing tiers

Go-to-market motion2 records

Distribution channels4 records

Marketing channels7 records

Core offering

True Circuits develops, markets, and licenses a broad range of analog/mixed-signal timing intellectual property, including Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), DDR PHYs, and the JSPICE Design Environment (JDE). Customers license silicon-proven hard macros (GDSII) and receive complete design kits (specifications, simulation models, timing libraries, layout abstracts, and LVS netlists) under mutual NDA, with attractive terms that do not require royalty payments. The IP is available in TSMC, GlobalFoundries, and UMC logic processes from 180nm down to 4nm.

Product overview

True Circuits develops, markets and licenses a broad range of PLLs (Phase-Locked Loops), DLLs (Delay-Locked Loops), DDR PHYs and other analog/mixed-signal Intellectual Property (IP). The company offers six general categories of PLL hard macros: Ultra+ PLLs (state-of-the-art LC PLLs with digital control algorithms), IoT PLLs (ultra-low power for wearables/sensors), General Purpose PLLs, Clock Generator PLLs, Spread Spectrum PLLs, and Deskew PLLs. Additionally, True Circuits offers synthesizable versions including the Precision PLL, micro PLL, and micro DLL for flexibility. The product line includes low-jitter Multi-slave DDR DLLs and Multi-phase DLLs. The DDR PHY is a high-performance, scalable system supporting LPDDR5, DDR4, LPDDR4, DDR3, LPDDR3, with automatic per-pin tuning and training. Supporting these hardware IP products is JDE (JSPICE Design Environment), an open design environment for circuit simulation, characterization, and cloud-based massively parallel simulations. All PLL and DLL hard macros are available in TSMC, GLOBALFOUNDRIES and UMC logic processes from 180nm to 4nm.

Differentiator

Problem solved

Functional benefit

Brands

• JDE (JDETM): JSPICE Design Environment - a powerful open design environment that accelerates the creation of complex analog and digital circuits.
• JSPICE
• True Partner Program

Products and services

• Ultra+ PLL State-of-the-art LC PLL using high-speed digital and analog circuits for exceptional performance. Features innovative digital control algorithm cutting lock time by up to 70%, ultra-low jitter (<100fs), ultra-wide multiplication range (1-250,000), precise frequency control with 26+ fractional bits, and programmable frequency spreading for FCC compliance. Sold as a silicon-proven hard macro IP to fabless semiconductor and ASIC/SoC designers.
• IoT PLL PLL specifically tailored for IoT market power requirements and wide frequency operation. Sips only 45uW at 30MHz, runs from core power, has multiplication factors up to 8192, and can clock a 32-bit CPU at up to 250MHz from a 32KHz crystal. Ideal for wearables and sensor devices. Sold as a silicon-proven hard macro IP to IoT chip designers.
• General Purpose PLL Wide range clock multiplier with deskew capability. Contains 1-16 divider at reference clock input, 1-64 divider in internal feedback path, and 1-16 divider at output. Delivers optimal jitter performance with 50% duty cycle outputs. Suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important. Sold as a silicon-proven hard macro IP.
• Clock Generator PLL PLL designed to multiply an input clock by an integer between 1 and 4096. Contains 1-64 divider at reference clock input, 1-4096 divider in internal feedback path, and 1-8 divider at output. Supports fractional-N multiplication with additional external low speed logic. 50% duty cycle outputs. Sold as a silicon-proven hard macro IP.
• Spread Spectrum PLL PLL designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability for PC and consumer electronics applications requiring low EMI. Provides precise and adjustable frequency spreading depths (1.5% typical, up to 10%) and rates (30KHz typical). Sold as a silicon-proven hard macro IP.
• Deskew PLL PLL designed to eliminate skew between output of clock distribution tree and clock reference. Can also multiply clock reference by integer between 1 and 4. Provides three 50% duty cycle skew-aligned outputs divided from internal VCO frequency by 1, 2, and 4. Sold as a silicon-proven hard macro IP.
• DDR DLL DLL using reference clock to establish time base for delaying arbitrary strobe signals by precise fractions of clock cycle. Uses phase-locked analog delay line which rejects temperature and supply voltage variations with high supply noise rejection. Can be configured with almost any number of slaves with single master section. Excellent linearity and very high resolution. Sold as a silicon-proven hard macro IP for DDR memory interface applications.
• Multi-Phase DLL DLL designed for high-speed interface applications. Generates precise multi-phase clocks directly from reference clock. Delivers optimal jitter performance over wide frequency range using analog delay-line architecture internally isolated from supply noise for very low output jitter. Provides duty cycle correction. Sold as a silicon-proven hard macro IP.
• Precision PLL (Synthesizable) Synthesizable PLL generating multiple precision clocks supporting any modulation scheme from almost DC to 10GHz. Outputs can be independently dynamically programmed cycle-by-cycle to any clock period. Clock frequency can be precise ratio of floating point numbers times reference frequency. Integrated phase noise better than 500ps RMS. Ideal for SerDes, processor and DVFS applications. Sold as a synthesizable IP core.
• micro PLL (Synthesizable) Small synthesizable general-purpose PLL multiplying reference clock by any integer or fractional-N value from 1 to 500K. Supports reference clock frequencies as low as 32KHz and output frequencies as high as 3GHz. Can stay locked while reference changes over 10:1 frequency range. Relatively low power, very fast locking, can quickly restart from sleep mode. Supports spreading and modulation profiles. Sold as a synthesizable IP core.
• micro DLL (Synthesizable) Small synthesizable DLL with master and multiple slaves topology. Supports reference frequencies typically in range of 500MHz to 3GHz and tracks reference changes over 8:1 frequency range while providing 9-bit accuracy in slave delay programming. Slave delays can be changed glitch-free. Very small zero code offset that can be precisely cancelled. Can quickly restart from sleep mode. Sold as a synthesizable IP core.
• TCI DDR PHY High-performance, scalable DDR PHY using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. Supports LPDDR5, DDR4, LPDDR4, DDR3, LPDDR3, is DFI 5.1 compliant, and includes fully automatic training managed by a special-purpose processor covering multi-cycle write leveling, read gate training, and per-pin read/write data eye training including PHY Vref and DRAM Vref settings. Sold as a hard macro IP to fabless semiconductor and SoC designers implementing high-speed DDR memory interfaces.
• JDE (JSPICE Design Environment) JDE is a powerful open design environment and ecosystem that accelerates the creation of complex analog and digital circuits by enabling designers to explore, automate and innovate. It includes JSPICE simulator, JANA sweep and measurement engines, JCHAR characterization engine, JPROBE analyzer, and cloud integration for massively parallel simulations. Made available to universities, businesses, and individual designers through a JDE membership program.

Quantifiable outcome

• Ultra+ PLL lock time reduced by as much as 70% over previous versions
• +5 more outcomes

Named customers7 records

Segments4 records

Ideal customer profiles3 records

Technology focussed Yes

API detail

Has API

No

API docs

API detail

Core technology

AI maturity

App detail

Integration1 record

Feature8 records

Partnerships

20 partnerships are on record, tiered regional, flagship, major, core and minor.

• Amos TechnologiesregionalChannel Partner/ Reseller/ DistributorIP distribution partner in Israel providing access to high-quality, silicon-proven timing hard macros to fabless semiconductor companies. Specializes in representing leading companies in Silicon IP and SoC design services.
• ArmflagshipStrategic or Co-development PartnerArm is the foundational platform for AI, delivering power-efficient, high-performance computing. Arm has the world's largest computing ecosystem including over 22 million developers.
• ChipEstimatemajorChannel Partner/ Reseller/ DistributorChipEstimate.com chip planning portal ecosystem with over 200 semiconductor design and verification IP suppliers and foundries. Serves diverse global audience of over 45,000 users.
• Design ReusemajorChannel Partner/ Reseller/ DistributorD&R operates the IP Market Place www.design-reuse.com for connecting SoC and integrated system designers with IP vendors. Delivers IP SoC News Alert newsletter to 40,000 community members.
• RambusmajorChannel Partner/ Reseller/ DistributorRambus delivers industry-leading chips and silicon IP for data center and AI infrastructure. Provides complementary timing IP through partnership with TCI.
• Micon GlobalregionalChannel Partner/ Reseller/ DistributorRepresents top-tier semiconductor, electronics, and software providers since 2001. Presence in UK, Europe, Israel, Japan, Taiwan and MENA, providing local expertise and support in EMEA and APAC regions.
• Pinnacle Design SystemsregionalChannel Partner/ Reseller/ DistributorFocused channel partner with offices in Shanghai, China, bringing leading-edge IP and IP-related technologies to Greater China region. Specializes in best-in-class SoC IP.
• ADTechnologycoreImplementation/ SI/ Consulting PartnerSouth Korea's largest system semiconductor design house with over 800 engineers and 800+ completed projects. Delivers ASIC design services across mobile, automotive, and HPC markets.
• Alchip TechnologiescoreImplementation/ SI/ Consulting PartnerLeading global provider of silicon design and production services for system companies developing complex and high-volume ASICs and SoCs. Headquartered in Taipei, Taiwan. Advanced 2.5D/3DIC and chiplet design capabilities.
• Faraday Technology CorporationcoreImplementation/ SI/ Consulting PartnerASIC solutions provider offering total 3DIC packaging, Neoverse CSS design, FPGA-Go-ASIC, and design implementation services. Extensive silicon IP portfolio including SerDes, USB, Ethernet, SATA, and PCIe.
• Global Unichip Corp. (GUC)coreImplementation/ SI/ Consulting PartnerLeading IC implementation and SoC manufacturing services provider using advanced process and packaging technology. Based in Hsin-Chu, Taiwan with global presence in North America, Europe, Japan, Korea, China, and Vietnam.
• HCL TechnologiescoreImplementation/ SI/ Consulting PartnerGlobal technology company with 227,000+ people across 60 countries. More than 30 years in semiconductors with strong ecosystem partnerships and digital accelerators.
• Muse SemiconductorminorImplementation/ SI/ Consulting PartnerProvides flexible multi-project wafer (MPW) services tailored for university researchers and early-stage innovators. Offers small minimum areas, frequent tapeouts, PDK and IP access.
• Progate Group CorporationcoreImplementation/ SI/ Consulting PartnerTaiwan-based ASIC design and turnkey service provider offering full-spectrum support from RTL to GDSII, wafer fabrication, packaging, and testing. TSMC Design Center Alliance member.
• VeriSiliconcoreImplementation/ SI/ Consulting PartnerPlatform-based, one-stop custom silicon services and semiconductor IP licensing. Headquartered in Shanghai, China with 9 design/R&D centers and 11 sales offices worldwide. Over 2,000 employees.
• ToppancoreImplementation/ SI/ Consulting PartnerDiversified global provider established in Tokyo in 1900. Home to 50,000+ employees delivering integrated solutions in printing, communications, security, packaging, electronics, and digital transformation.
• TessolvecoreImplementation/ SI/ Consulting PartnerLeading provider of end-to-end engineering services across semiconductor value chain from chip architecture, design, test development and embedded systems. Founded in 2004 in Bangalore, India with presence in 10+ countries serving 9 of top 10 tech companies.
• TSMCflagshipTechnology or IntegrationWorld's leading dedicated semiconductor foundry. TSMC works with True Circuits to ensure PLL and DLL IP families are ported, silicon tested and available early in advanced process technologies. Close technical and business relationships enable common customers to get early access to timing technologies.
• GlobalFoundriesmajorTechnology or IntegrationLeading manufacturer of essential semiconductors enabling AI at scale. Partnership ensures TCI timing IP is available in GF processes for automotive, aerospace, data center, IoT and other high-growth markets.
• UMCmajorTechnology or IntegrationLeading global semiconductor foundry providing high-quality IC fabrication services. Partnership ensures TCI timing IP availability in UMC processes including Logic/Mixed-Signal, embedded High-Voltage, and BCD technologies.

Scale indicators7 records

Recent moves7 records

Expansion highlights6 records

Direct peers

• Silicon Creations: Silicon Creations develops and licenses analog and mixed-signal IP, including PLLs, DLLs, and SerDes, for fabless semiconductor customers — directly comparable to True Circuits' PLL/DLL/timing IP portfolio.
• Analog Bits: Analog Bits designs and licenses clocking IP, PLLs, sensors, and SerDes for SoCs/ASICs, directly competing with True Circuits in the timing and analog IP market.
• Rambus: Rambus is a direct distribution partner of TCI but also licenses its own memory and interface IP, making it a comparable peer in the high-speed interface / DDR PHY space.
• Mobiveil: Mobiveil develops and licenses memory controller, DDR PHY, and interface IP — directly comparable to True Circuits' DDR PHY and timing IP product line for ASIC/SoC designers.

Broad incumbents

• Synopsys: Synopsys is a broad EDA and IP incumbent whose DesignWare portfolio includes analog/mixed-signal and interface IP that overlaps with True Circuits' PLL, DLL, and DDR PHY offerings.
• Cadence Design Systems: Cadence is a broad EDA and IP incumbent; its IP group offers analog, mixed-signal, and interface IP that competes with True Circuits' timing IP portfolio across fabless and ASIC customers.
• Silicon Labs: Silicon Labs is a broad incumbent in timing ICs (e.g., Si534x clock generators), offering silicon-based clocking solutions comparable in functional category to TCI's PLL IP, though delivered as discrete ICs rather than licensable IP cores.

Emerging players

• Agnisys: Agnisys provides EDA tools for IP and SoC design automation, with partial overlap to True Circuits' JDE/JSPICE Design Environment expansion into analog/digital design tooling.
• Avery Design Systems: Avery Design Systems offers verification IP and related EDA tooling for memory and interface protocols, partially overlapping with True Circuits' DDR PHY and timing IP verification ecosystem.

Others

• Renesas Electronics: Renesas is both a TCI customer (using TCI's clock generator PLL for 10 Gbps SONET/SDH ASICs) and a manufacturer of timing/clocking ICs, making it an adjacent ecosystem participant with bidirectional relevance.

Market position

Strengths5 records

Weaknesses5 records

Competitive moat5 records

Key risks7 records

Key highlights7 records

Customer concentration

Revenue estimate

Valuation estimate

Number of profiles

Profiles3 records

Funding overview

Funding rounds

Investors

Funding detail is available on the Subscription and Enterprise plan.Contact sales →

M&A

Investments

M&A and investment is available on the Subscription and Enterprise plan.Contact sales →

Frequently asked questions about True Circuits, Inc.